PSoC5LP: Why can't I fit this UART into my available UDB?

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KyTr_1955226
Level 6
Level 6
250 sign-ins 10 likes given 50 solutions authored

Hey all,

I've got a project in the works that uses 3 UARTs.  I manage to fit in the 3 required, but I want to add a 4th for debugging purposes if possible.  This should be no problem, as I appear to have adequate UDB resources for a half-duplex UART according to the UART component datasheet:

KyTr_1955226_0-1618329089280.png

KyTr_1955226_1-1618329144785.png

However when I try to build, I'm running out of UDBs during placement.  Looks like running out of macrocells?  I'm curious as to why this is?  Something to do with how macrocells get allocated maybe?

I'm using PSoC Creator 4.3, the PSoC5LP part is a CY8C5667AXI-LP040.  I've attached the report file to this post.  DBG_UART is the component name for the half-duplex I am trying to add.  I had to put it in a .zip because apparently I can't upload .rpt or .txt files.

Appreciate any thoughts,

Thanks!

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1 Solution
RodolfoGL
Employee
Employee
250 solutions authored 250 sign-ins 5 comments on KBA

Hi all,

It is actually impossible to use 100% of the Macrocells or Pterms. Due to routing restrictions, you might not be able to use all the inputs/outputs of the PLDs. Said that, if you reach around 85~90% of a Macrocells or Pterms, the placer might not be able to fit your design.

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