MaMi,
What you are asking for is easier said than done.
It would be significantly easier if the SPI_done signal in the Tx interrupt selection came out with the timing shown in the Functional description of the datasheet. As it is, the timing is basically the same as the signal SS.
Another solution is to modify the B_SPI_Master_v2_50.v Verilog description file. If someone out there wants to tackle this, be my guest.
I have another approach. It is not optimal and the last bit is latched (sort of).
Here's a clip of the modified SPIM circuit.
You'll notice a Control Register (CR_data). When SS is deasserted (inactive high) the data in CR_data is placed on MOSI by selecting the Mux=0.
Here is a code fragment to make this happen:
SPIM_WriteByte(txBuffer[i]); /* Sends the next data to the SPIM */
CR_data_Write(txBuffer[i]); /* Sets the 'latched' lsb */
The "sort of" is the if the last bit is HIGH, the SS going inactive is 1/2 SCLK from the last bit going LOW at the end of the SPI transmission. This provides a 1/2 SCLK of a LOW before it goes high again. If this is a problem, this solution is not for you.
Here are two pics of txBuffer being sent of 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07.
The second scope pic is zoomed version of the 0x07 being sent.
