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PSoC 5, 3 & 1 MCU

MaMi_1205306
Honored Contributor

Dear Sirs and Madams,

 

We are considering the SPI master component of PSoC5LP.

In the SPI Master component, we would like to keep the last state that MOSI sent 1 Byte.

 

Specifically,

After sending xxxx xxx0,  the output of mosi is fixed to 'L'

After sending xxxx xxx1,  the output of mosi is fixed to 'H'

 

The model number of PSoC5LP is CY8C5468AXI-LP106.

I think there is a way to use a latch circuit and a way to use a custom component by UDB.

What do you think is the optimal solution?

 

Regards,

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1 Solution
Len_CONSULTRON
Honored Contributor II

MaMi,

What you are asking for is easier said than done.

It would be significantly easier if the SPI_done signal in the Tx interrupt selection came out with the  timing shown in the Functional description of the datasheet.  As it is, the timing is basically the same as the signal SS.

Another solution is to modify the B_SPI_Master_v2_50.v Verilog description file.  If someone out there wants to tackle this, be my guest.

I have another approach.  It is not optimal and the last bit is latched (sort of).

Here's a clip of the modified SPIM circuit.

Len_CONSULTRON_0-1625580420827.png

You'll notice a Control Register (CR_data).  When SS is deasserted (inactive high) the data in CR_data is placed on MOSI by selecting the Mux=0.

Here is a code fragment to make this happen:

 

SPIM_WriteByte(txBuffer[i]); /* Sends the next data to the SPIM */
CR_data_Write(txBuffer[i]);  /* Sets the 'latched' lsb */

 

The "sort of" is the if the last bit is HIGH, the SS going inactive is 1/2 SCLK from the last bit going LOW at the end of the SPI transmission.  This provides a 1/2 SCLK of a LOW before it goes high again.  If this is a problem, this solution is not for you.

Here are two pics of txBuffer being sent of 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07. 

PRINT_18.png

The second scope pic is zoomed version of the 0x07 being sent.

PRINT_19.png

 

Len
"Engineering is an Art. The Art of Compromise."

View solution in original post

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2 Replies
Len_CONSULTRON
Honored Contributor II

MaMi,

What you are asking for is easier said than done.

It would be significantly easier if the SPI_done signal in the Tx interrupt selection came out with the  timing shown in the Functional description of the datasheet.  As it is, the timing is basically the same as the signal SS.

Another solution is to modify the B_SPI_Master_v2_50.v Verilog description file.  If someone out there wants to tackle this, be my guest.

I have another approach.  It is not optimal and the last bit is latched (sort of).

Here's a clip of the modified SPIM circuit.

Len_CONSULTRON_0-1625580420827.png

You'll notice a Control Register (CR_data).  When SS is deasserted (inactive high) the data in CR_data is placed on MOSI by selecting the Mux=0.

Here is a code fragment to make this happen:

 

SPIM_WriteByte(txBuffer[i]); /* Sends the next data to the SPIM */
CR_data_Write(txBuffer[i]);  /* Sets the 'latched' lsb */

 

The "sort of" is the if the last bit is HIGH, the SS going inactive is 1/2 SCLK from the last bit going LOW at the end of the SPI transmission.  This provides a 1/2 SCLK of a LOW before it goes high again.  If this is a problem, this solution is not for you.

Here are two pics of txBuffer being sent of 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07. 

PRINT_18.png

The second scope pic is zoomed version of the 0x07 being sent.

PRINT_19.png

 

Len
"Engineering is an Art. The Art of Compromise."

View solution in original post

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MaMi_1205306
Honored Contributor

Len-san,

 

Sorry for the late reply for confirmation.

It seems that it can be realized by the proposal using your ControlReg and DMUX components.

If this circuit has timing issues, consider custom components with Verilog.

 

Thank you,

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