I am taking current measurements of my PSoC5LP running under different conditions right now. The power estimator spreadsheet seems to underestimate the contribution caused by increasing the Bus Clock.
In the spread sheet there is a field for CPU Speed, if I program the PSoC5LP to run at 12 MHz, the current that I measure is what I would expect if I was running at 24 MHZ. If I increase the Bus Clock to 24 MHz, I measure a current similar to what the spreadsheet estimates at 48 MHz.
Is the CPU Clock really twice the bus clock? If this is so, can someone show me were this is documented at?
Thanks a ton!
All the clocks are set in the design-wide resources. There is no magic '2x' somewhere.
How are you measuring the current? Are you sure there are no other components that might influence the measurements? Are you using your own board, or one of the dev kits? Also, did you compare the values in the spreadsheet with what the data sheet for your device says?
Sorry for not replying back sooner. The PSoC5LP is part of my own custom board, when I took the measurements, the main supply voltage was regulated down from 2.0 V from the source meter down to1.8V using the analog and digital voltage domain LDOs on the board. I have disabled the external regulators and the debug interface (and unplugged debug cable), The measurments were taken with the PSoC5lp in a while 1 loop.
The datasheet claims that I should be drawing between 5.4-7 mA with the CPU running at 12 MHz. At 12 MHz, I am drawing 11.4 mA. The datasheet claims that at 48 MHz that I should draw 15.4-17 mA and I am measuring 26.7 mA.
I don't see a reason why the supply current should scale the way it did. If I had some other board components drawing more current than I expected, I would imagine that their current would draw would stay constant as a function of CPU clock speed. What I measured shows that at higher CPU frequencies, that I am getting further away from the specified values.
I have ensured that all of the external components on my board were in their low power state before taking the current measurements, and have not noticed a significant difference in current.
Which chip are you using? The number you are seeing look like an old PSoC5 (non-LP) chip, which is unlikely... And are you indeed sure that all peripherals are in low-power state? Best would be to measure current in a place where you only measure the PSoC chip (like the Pioneer kits do).
Also, note that the peripherals in the PSoC itself can draw additional current (mots noticeable is ethe DFB block which could draw up to 40mA at 80MHz). You need to look through all of nthe ones you are using and check how much current they draw (I'm not sure whether all or in the family DS, or in the component DS).
I am using the CY8C5868LTI-LP038. I ran through all of the generated header files and called every sleep function before taking the measurement save for a SPI interface which was never used. I don't have any logic connected to a clock in my top design file that should be consuming power when I go to sleep.
Other than the PSoC itself, on my board, the major current consumers are a radio transceiver, analog filter, and flash memory chip. The flash memory was reset and put in standby mode, the radio was put in standby, and I was able to measure the current reducing when I turned off my analog filter.
I pulled up the psoc resource summary and did not see anything I wouldn't expect like the DFB being used or all of the UDBs being grabbed. I just don't see a reason for the operational current to increase the way it does when I speed up the PSoCs CPU clock.
Well, if its not one of the peripherals, then you best chance is to file a support case with Cypress. In my experience they are quite fast and helpful. Look in the top-right corner, "Mycases". (and maybe report back what came out of this...)
Will do thanks. It might be a while before I get back around to the end of this as my next week will be out of control, but hopefully I can get the ball rolling on this at least.