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PSoC 5, 3 & 1 MCU

MaMi_1205306
Honored Contributor

Hi,

We would like to confirm for mode of contorl registor.

Because the detailed timing is not described in the data sheet.

pastedImage_0.png

We understand that direct mode is output at the edge of the master clock when it is set asynchronously from the CPU.

pastedImage_1.png

We understand that Sync mode is output on the rising edge of the clock.

The master clock and clock are asynchronous.

Is the recognition so far correct?

pastedImage_3.png

Use Sync mode,
What happens if the clock input to Sync mode is synchronized to the master clock?

(a) Output in synchronization with the master clock and the clock.(Blue line)
(b) The master clock and clock can not be synchronized, so It is output at the clock after the master clock.(Red line)

(c) (a) or (b) operation, Is it prohibited to synchronize the master clock and the clock because it is metastable?

Regards,

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1 Solution
JobinT_31
Employee

Please find the control register working shown in below figures. (Architecture TRM '21.3.3.2 Control Register Operation') - https://www.cypress.com/file/123561/download

pastedImage_1.png

Sync mode:

pastedImage_2.png

In original post the red line is correct for the third figure. As per above figure(21-33) if the Bus Write Clock(Master clock) and SC CLK(Clock) is at the same time. The Data bus change cannot come to 'To routing'(OutSync) in the same clock. The second flipflop in the above figure samples the old data on its first clock.

For response 4. The outsync will change on the first positive edge of 'clock'

Response 5 both the figures seems correct.

Conclusion: If Bus Write Clock and SC CLK positive edge comes at the same time, there is always 1 SC clock delay expected for the output.

If the SC clock positive edge is delayed by 'n' time from the Bus Write Clock. The output can change on first SC clock if the 'n' time is greater than the total propagation delay of first Flipflop. It will be safe to assume the propagation delay is less than the (1/HFCLK)maximum clock the chip supports.

Thanks

Jobin GT

View solution in original post

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7 Replies
odissey1
Honored Contributor II

user_23...,

I believe that in all three examples there is some misconception regarding when "Set Data" takes place. On drawings provided it depicted somehow 90 deg  to/from the rising edge of the Master Clock. But all CPU events "quantize" on the Master Clock, and "Set Data" is written with bus clock, taking place on the rising edge of the Master Clock as well.

I am less sure about "metastability" answer. My bet that in such case when "Set Data" and Clock_1 coincide at the same rising edge of the Master Clock (metastability event), the output of the Control Register should wait for the next tick of the Clock_1. According to the Datasheet it is "single-synched", which means one SC clock delay (single DFF register).

/odissey1

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MaMi_1205306
Honored Contributor

Thank you for your reply.

A clock synchronized with the master clock is generated by RTL.

pastedImage_5.png

When the above timing comes,

What happens to the output timing of the control register?

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odissey1
Honored Contributor II

I updated my post above, I believe that red line is correct (one SC clock delay)

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MaMi_1205306
Honored Contributor

pastedImage_2.png

I am sorry to confirm it many times.
Is the above timing when it is One SC Delay?

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odissey1
Honored Contributor II

I believe that in case of metastability, the RED line is correct:

pastedImage_1.png

When there is no metastability:

pastedImage_0.png

Again, this is only my "belief"

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MaMi_1205306
Honored Contributor

We would like to read the output of the control register in RTL(custom logic of UDB),

but the signal input to the clock of the control register is a signal synchronized to the master clock by RTL.
It is difficult that the timing of the details is not described in the data sheet.

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JobinT_31
Employee

Please find the control register working shown in below figures. (Architecture TRM '21.3.3.2 Control Register Operation') - https://www.cypress.com/file/123561/download

pastedImage_1.png

Sync mode:

pastedImage_2.png

In original post the red line is correct for the third figure. As per above figure(21-33) if the Bus Write Clock(Master clock) and SC CLK(Clock) is at the same time. The Data bus change cannot come to 'To routing'(OutSync) in the same clock. The second flipflop in the above figure samples the old data on its first clock.

For response 4. The outsync will change on the first positive edge of 'clock'

Response 5 both the figures seems correct.

Conclusion: If Bus Write Clock and SC CLK positive edge comes at the same time, there is always 1 SC clock delay expected for the output.

If the SC clock positive edge is delayed by 'n' time from the Bus Write Clock. The output can change on first SC clock if the 'n' time is greater than the total propagation delay of first Flipflop. It will be safe to assume the propagation delay is less than the (1/HFCLK)maximum clock the chip supports.

Thanks

Jobin GT

View solution in original post

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