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PSoC 5, 3 & 1 MCU

ViDv_264506
Contributor II

Hi, 

(How) Is it possible on PSoC5LP to DMA transfer 32 bytes from DWT_CYCLE_COUNT 0xE0001004 to RAM.

Viktor

 

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1 Solution
Len_CONSULTRON
Honored Contributor II

Viktor,

I performed a little more investigation.

I placed some error detection code in the DMA initialization function:

 

void DMA_memcpy_Init(void)
{
volatile uint8_t dmaerror;
volatile uint32_t dmaerroraddr;
	
	
	DMA_memcpy_Chan = DMA_memcpy_DmaInitialize(DMA_memcpy_BYTES_PER_BURST, DMA_memcpy_REQUEST_PER_BURST, 
	    HI16(DMA_memcpy_SRC_BASE), HI16(DMA_memcpy_DST_BASE));
	DMA_memcpy_TD[0] = CyDmaTdAllocate();
	CyDmaTdSetConfiguration(DMA_memcpy_TD[0], 4, DMA_memcpy_TD[0], CY_DMA_TD_AUTO_EXEC_NEXT | DMA_memcpy__TD_TERMOUT_EN);
	CyDmaTdSetAddress(DMA_memcpy_TD[0], LO16((uint32)CYREG_NVIC_CPUID_BASE), LO16((uint32)&mem_dst_));
	CyDmaChSetInitialTd(DMA_memcpy_Chan, DMA_memcpy_TD[0]);
	CyDmaChEnable(DMA_memcpy_Chan, 1);
	if( (dmaerror = CyDmacError()) > 0)
	{
		dmaerroraddr = CyDmacErrorAddress();
		CyDmacClearError(dmaerror);
	}
}

 

When executing CyDmaChEnable() I get a return error of (0x4 = CyDmacError()):

Bit 2 CY_DMA_UNPOP_ACC Set to 1 when an access is attempted to an invalid address. Cleared by writing a 1.

When I execute  CyDmacErrorAddress() the address returned is CYREG_NVIC_CPUID_BASE.

It appears that the DMA HW cannot access the addresses at CYDEV_ITM_BASE.

Therefore unless Cypress has other information, then

"Is it possible on PSoC5LP to DMA transfer 32 bytes from DWT_CYCLE_COUNT 0xE0001004 to RAM."

NO

Len
"Engineering is an Art. The Art of Compromise."

View solution in original post

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8 Replies
Len_CONSULTRON
Honored Contributor II

ViDv,

I believe what you are looking to do is possible.

However ... isn't DWT_CYCLE_COUNT only 32 bits not bytes?

Len
"Engineering is an Art. The Art of Compromise."
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ViDv_264506
Contributor II

Clear,

DWT_CYCLE_COUNT is 32 bits wide register ..... not bytes. My overtyping....

Viktor

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Len_CONSULTRON
Honored Contributor II

Viktor,

I've attached a starter project for your DMA of DTW_CYCLE_COUNT. 

I believe it takes a snapshot of the DTW_CYCLE_COUNT ten times a second.  It then pushes the data collected to the Terminal 10 times a second.

I have no good way right now to verify its operation.  It's a good starting point for your effort.

Len
"Engineering is an Art. The Art of Compromise."
ViDv_264506
Contributor II

Dear Len, 

many thanks. I start now testing. I let you now  ......

Best regards,

Viktor

 

 

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ViDv_264506
Contributor II

Dear Len, 

I have tested your example  ...... does not function for many reasons.

In the attatchment you find modified Cypress AN52705 examle, which is OK in flash to RAM DMA transfer and which is OK in RAM to RAM transfer.  Please use my example in debug mode for testing on CY8CKIT-059 variants are masked.

DWT_CYCLE_COUNT (0xe0001004) CAN NOT be used as source........ Why?

Best regards,

Viktor

 

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Len_CONSULTRON
Honored Contributor II

Viktor,

You are correct it is not working.

As a sanity check, I changed the source address from  DWT_CYCLE_COUNT to NVIC_CPUID_BASE.

NVIC_CPUID_BASE is basically a constant (0x31C22F41).  My Terminal display definitively was not constant.

Hopefully someone with more DMA experience can join this thread and tell us what is needed. 

Len
"Engineering is an Art. The Art of Compromise."
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Len_CONSULTRON
Honored Contributor II

Viktor,

I performed a little more investigation.

I placed some error detection code in the DMA initialization function:

 

void DMA_memcpy_Init(void)
{
volatile uint8_t dmaerror;
volatile uint32_t dmaerroraddr;
	
	
	DMA_memcpy_Chan = DMA_memcpy_DmaInitialize(DMA_memcpy_BYTES_PER_BURST, DMA_memcpy_REQUEST_PER_BURST, 
	    HI16(DMA_memcpy_SRC_BASE), HI16(DMA_memcpy_DST_BASE));
	DMA_memcpy_TD[0] = CyDmaTdAllocate();
	CyDmaTdSetConfiguration(DMA_memcpy_TD[0], 4, DMA_memcpy_TD[0], CY_DMA_TD_AUTO_EXEC_NEXT | DMA_memcpy__TD_TERMOUT_EN);
	CyDmaTdSetAddress(DMA_memcpy_TD[0], LO16((uint32)CYREG_NVIC_CPUID_BASE), LO16((uint32)&mem_dst_));
	CyDmaChSetInitialTd(DMA_memcpy_Chan, DMA_memcpy_TD[0]);
	CyDmaChEnable(DMA_memcpy_Chan, 1);
	if( (dmaerror = CyDmacError()) > 0)
	{
		dmaerroraddr = CyDmacErrorAddress();
		CyDmacClearError(dmaerror);
	}
}

 

When executing CyDmaChEnable() I get a return error of (0x4 = CyDmacError()):

Bit 2 CY_DMA_UNPOP_ACC Set to 1 when an access is attempted to an invalid address. Cleared by writing a 1.

When I execute  CyDmacErrorAddress() the address returned is CYREG_NVIC_CPUID_BASE.

It appears that the DMA HW cannot access the addresses at CYDEV_ITM_BASE.

Therefore unless Cypress has other information, then

"Is it possible on PSoC5LP to DMA transfer 32 bytes from DWT_CYCLE_COUNT 0xE0001004 to RAM."

NO

Len
"Engineering is an Art. The Art of Compromise."

View solution in original post

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ViDv_264506
Contributor II

Dear Len, 

many thanks for DMA error diagnostics. It is practical.

Best regards,

Viktor

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