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PSoC 5, 3 & 1 MCU

Anonymous
Not applicable

PSoC 5lp ADC_SAR_Seq does not update readings correctly. The first conversion after reset
or programming seems to be correct but on subsequent reads the first channel updates on each
conversion, but the second channel only updates on every OTHER conversion. Does anyone else
have the same result??? I have tried both the software call ADC_SEQ_StartConvert and the hardware
conversion with a control register results same both ways. I also tried reading the finalResult
variables also same result.

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1 Solution
JoMe_264151
Expert II

Will you please upload the complete project, so we all can have a look at?

   

To do so, use Creator -> File -> Create workspace bundle (minimal) and attach the resilting .zip file here (DO NOT use chrome, that will not work)

   

 

   

Bob

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13 Replies
JoMe_264151
Expert II

Will you please upload the complete project, so we all can have a look at?

   

To do so, use Creator -> File -> Create workspace bundle (minimal) and attach the resilting .zip file here (DO NOT use chrome, that will not work)

   

 

   

Bob

View solution in original post

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Anonymous
Not applicable
        Workspace bundle   
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JoMe_264151
Expert II

Two points I have found at first look:

   

Interrupts connected to USB-components should be set to "Rising Edge", yours are set to "Derived" which works for FF blocks, see in datasheet for the Interrupt-component.

   

 

   

The start-signal for the SAR must be synchronized to the input-clock as the datasheet says. Sou you'll have to use an external clock and a sync-component to fulfill this requirement.

   

 

   

Bob

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Anonymous
Not applicable
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ETRO_SSN583
Esteemed Contributor

For myself, I found some confusing explanations over type of interrupt,

   

when to use derived vs rising vs level. This ap note covers that fairly well -

   

 

   

    

   

          http://www.cypress.com/?rID=38267    AN54460     Pages 5 - 7

   

 

   

Regards, Dana.

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JoMe_264151
Expert II

Excerpt from isr datasheet:

   

   

When connected to fixed-function interrupt outputs, the type should be set to DERIVED. For

   

other interrupt sources, you should usually choose RISING_EDGE to capture an event (for

example, periodic clock) and LEVEL for a state (for example, FIFO fill levels). For DMA NRQ

signals, any of the settings produce the same result of a single interrupt for each NRQ event.

   

   

 

   

Bob

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Anonymous
Not applicable

To clarify further:

   

I first tried to use the component in its default state. Internal clock, internal IRQ, and software triggered read.

   

This at first appears to work, but careful examination reveals the second channel only updates on every other cycle,

   

I does appear to give the correct result after a reset (first cycle) or after re-programming.

   

Next I added an external isr (not using the built in one) no change In result.

   

Lastly I tried a hardware trigger and synced w/ bus clock again same result.

   

reversing the order of reading the channels same result. I have not tried reading three channels and discarding the third.

   

"I kinda think the thing's broke"  I will try a few more things and post again if I learn anything else. The other fellow trying

   

to send results out the serial port has what seems to me to be the same problem with ADC_SAR_Seq.

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ETRO_SSN583
Esteemed Contributor

You might consider posting a case with a link to your post here.

   

 

   

    

   

          

   

To file a tech case -

   

 

   

www.cypress.com

   

“Support”

   

“Technical Support”

   

“Create a MyCase”

   

 

   

Regards, Dana

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Anonymous
Not applicable

In you ISR you start the ADC then read the results. Would it be read the result first and start the conversion for next cycle? 

   

Nor sure if that helps?

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Anonymous
Not applicable

Thanks to all who took the time to look at my problem. I have created a MyCase and tech support responded that config looks OK and they will pass it along to someone who will try to duplicate my result. I will post again when there is anything to report.

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Anonymous
Not applicable

To all who may be interested I am posting a simple project that demonstrates to issue I have found. Connect a pot to the two channels defined in the project and observe the results on the LCD when the voltage is varied. (CY8C_Kit-001) The second channel lags the first by one conversion. This may have minimum effect in many applications, but it does represent a phase shift between the two channels when sampling a time-variable signal.

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JeCo_264681
Contributor

When comparing two or more samples "simultaneously" with a SAR Sequencer or with a MUX, we must realize that the samples are not really taken simultaneously for all channels.  They are time shifted by the MUX.  Fortunately, there is a way to time align (phase align) multiple samples using a FIR Filter.  This concept is addressed in these two papers by Kendall Castor-Perry:

   

http://www.cypress.com/?docID=45637
http://www.cypress.com/?docID=34227

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ETRO_SSN583
Esteemed Contributor

There is nothing stopping you from using S/H front ends to effect

   

simultaneous sampling. But at 1 MSPS you have to pay a lot of

   

attention to the signal path, see attached ap notes.

   

 

   

Regards, Dana.

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