Sounds like you are observing noise. If you short the
input then you will see just noise on the output. Several
1) Thermal due to fdbk R's used
2) Noise due to PSRR
3) Noise due to layout and bypassing
4) Internal/external noise due to C coupling effects
To investigate -
1) If you have a spectrum analyzer look at output noise to determine
largest fundamental components, then examine if thats correlated to
an internal clock or divider or pin bit banging. Turn off all internal UDB
digital and other system resources, one at a time, to see what internal
resource may be largest contributor.
2) Caps, best bulk caps bypassing are polymer tantalums paralled my ceramics.
3) Look at any hi z nodes in signal path, they will be susceptable to coupling via
4) If driving high C loads, like gate of external MOSFET, look at return current
paths, make sure they are "stiff".
5) Using scope on infinite persistance look at supply rails, to get an idea of
what pk-pk noise levels you are dealing with.
Thtas true if sign of input offset is +, otherwise the results quite different.
You can always measure the offset with A/D, and subtract it out. Thats because
DelSig CM in is 100 mV ouytside the rails.
The beauty of PSOC, ability to do a lot of self test.
Out of curiosity - how can I measure the (internal) offset voltage of an OpAmp? (Apart from shorting the inputs and then measuring the output)