PSoC versus Kit environmental robustness: Might I2C issues at temperature be due to kit?

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GrCa_1363456
Level 6
Level 6
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Using a PSoC 5 kit, CY8CKIT-059, the I2C running at 100kHz occasionally locks up at extreme cold ~ -25 to -40.

Are there know issues with the PSoC 5 at low temperatures or should I focus on the CY8CKIT-059 kit as the potential issue?

When the I2C locks up, it reports receiving 0 and won't work properly until power is recycled.

The problems go away when I2C speed is dropped to 50kHz.

Greg

 

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GrCa_1363456
Level 6
Level 6
50 likes received Beta tester First comment on KBA

PSoC Creator had auto-assigned the I2C lines into different quadrants. Communication over that I2C works without issue under most conditions. The un-ideal routing appears to be the likely culprit of issues at the temperature extreme.

Thank you both for your support.

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Len_CONSULTRON
Level 9
Level 9
Beta tester 500 solutions authored 1000 replies posted

Greg,

What are the I2C devices that the PSoC is talking to?

I'm assuming the PSoC is the I2C master.

Len
"Engineering is an Art. The Art of Compromise."
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BiBi_1928986
Level 7
Level 7
First comment on blog 500 replies posted 250 replies posted

Hello GrCa.

Several KIT-059 GPIO pins are connected to capacitors.
Check the KIT-059 schematic to ensure you are not using a GPIO with a capacitor hanging on it.  If you have connected I2C to one of these GPIO's, you can either remove the capacitor or use a different GPIO.

Are you operating KIT-059 at 5V or 3.3V?
What voltage is your I2C device operating at?

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GrCa_1363456
Level 6
Level 6
50 likes received Beta tester First comment on KBA

Thank you both for the suggestions.

PSoC is running at 5V as is the external I2C device.

SCA is using P12-5; SCL is using P2-3. These were auto-selected by PSoC Creator. As I'm not using the I2C in sleep mode, the TRM notes any pins are acceptable. The pins are configured for Open Drain, Drives Low as recommended in section 26.3.3 of the TRM. External pullup of 2k supports higher speeds per table 7-2 of the datasheet assuming not unusual capacitance on the line, which I don't see.

Are there any tools that estimate internal timing in the PSoC?

I don't see anything that indicates potential violation of timing; but I'm curious if the design might be pushing some timing limits based on internal component placement, pin routing and resource utilization. 

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Hello.

Sounds like you've done your home work.

There's a Build Config setting (or it might be under design wide resources) that allows you to set the temperature range.  Make sure it's set to -40C.

As Len asked, what I2C devices are you using?

How long are the I2C wires?

Do you have decoupling capacitors across the I2C device power/ground pins?

Suggestion: you could try the 5LP built-in I2C port instead of UDB implementation to see if you get different results. 

Gary,

Are there any tools that estimate internal timing in the PSoC?

When you perform the Application Build phase, it generates a timing report. called "<proj_name>_timing.html"

I provides the internal worst-case timing analysis based on the selected temp range.  Default temp range: -40C to 85C.

Also the Application Build phase warns if there is a possible timing violation.

I hope this is about what you were inquiring.

 

Len
"Engineering is an Art. The Art of Compromise."
GrCa_1363456
Level 6
Level 6
50 likes received Beta tester First comment on KBA

PSoC Creator had auto-assigned the I2C lines into different quadrants. Communication over that I2C works without issue under most conditions. The un-ideal routing appears to be the likely culprit of issues at the temperature extreme.

Thank you both for your support.

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Greg,

Interesting!

It is a known issue that arbitrary routing of analog signals could be non-optimal.  This is because non-optimal routing could add >500 ohms of routing resistance in the signal path which can be an issue at temperature extremes.

However, it is my understanding that the UDB blocks use a digital crosspoint datapath connection scheme is should be at least mostly immune to temperature extremes.  The I2C implementation is fully digital.  The only exception to this is that if internal pullups are used for the SDA or  SCL lines, the pull-up resistor could have a large variance in resistance value at the extremes.   This would adversely affect the rise-time factors at the higher (100Kbps) data rate.

Hopefully someone from Cypress can weight in on my understanding.

Len
"Engineering is an Art. The Art of Compromise."
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