Attached is a demo of Lock-in detector which can operate in 100Hz - 10kHz range. It utilizes built-in modulator stage of PSoC5 DelSig_ADC. The Device Under Test is a simple bridge with a trimpot, producing differential output in the range 0-1V. The demo shows three ways of filtering ADC data stream: (1) directly filtering ADC data using first-order IIR filter and ADC interrupt; (2) using DMA to transfer ADC data to digital Filter (and polling Filter output); (3) further decimating data from Filter output (on interrupt) and passing it through another IIR filter. All three results are displayed using plotting software (Multichart) at 100 samples/sec, allowing to compare results.
Project utilizes several custom components: DDS24 (tunable freq. and phase generation), QuadDecoder_SW (for interfacing to a rotary shaft encoder to change frequency and phase), CY8KIT-059 off-chip annotation library. They must be loaded into Project->Dependencies. Use links below to download them:
DDS24: 24-bit DDS arbitrary frequency generator component
Quad Decoder with Button Switch component for rotary shaft encoders
Annotation library for CY8CKIT-059 Prototyping Kit
Attached below are project file, Multichart GUI, and screenshots demonstrating noise level for 200mV p-p input signal, and response time for 0-200mV ramp. Note that most noise originates from USB power fluctuations on (digital) driving pins.
odissey1
