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PSoC 5, 3 & 1 MCU

RoRo_4659551
New Contributor II

Hi,

I am trying to configure multiple pins connected to interrupts but I receive an error [see attached pictures].

RoRo_4659551_1-1620121963019.png

 

RoRo_4659551_2-1620121972232.png

 

RoRo_4659551_0-1620121952291.png

 

Thanks,

Roy Roif

 

@Motoo_Tanaka 

 

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6 Replies
MotooTanaka
Esteemed Contributor

Hi,

The user reference you addressed was my private CDC account.

Please refer to the following reference

https://community.cypress.com/t5/user/viewprofilepage/user-id/15414

 

Now returning to your question.

The pin interrupt structure of arm Cortex-M is per port and not per pin.

P0[0] ~ P0[7] share same interrupt.

So in your cate P5[0] ~ P5[7] share same interrupt.

And you/we need to determine which pin generated the interrupt in ISR.

(or  check the interrupt source)

I tried a sample with CY8CKIT-059 (CY8C5888LTI-LP097] and as I could not use P5[x]

I used P3[0] ~ P3[4].

schematic

002-schematic.JPG

Pin configure (of DIN)

I bundled 5 pins into 1 pin(s) component with 1 irq.

To use falling event as interrupt, I configured the pin resistor pull-up.

003-pin_config1.JPG

And I set Interrupt Falling edge.

004-pin_config2.JPG

Pins

005-Pins.JPG

main.c

#include "project.h"
#include "stdio.h"

#define STR_BUF_LEN 64
char str[STR_BUF_LEN+1] ;
void print(char *str)
{
    UART_PutString(str) ;
}

volatile int pin_intr_flag = 0 ;
volatile uint8_t pin_intr_src=0 ;

CY_ISR(pin_isr)
{
    pin_intr_flag = 1 ;
    pin_intr_src=DIN_ClearInterrupt() ;
}

void init_hardware(void)
{
    CyGlobalIntEnable; /* Enable global interrupts. */
    UART_Start() ;
    print("\x1b[2J\x1b[;H") ;
    print("PSoC 5LP Pin Interrupt Test ") ;
    snprintf(str, STR_BUF_LEN, "(%s %s)\n\r", __DATE__, __TIME__) ;
    print(str) ;
    
    /* DIN_INTR_ALL or DIN_0_INTR | DIN_1_INTR | DIN_2_INTR | DIN_3_INTR | DIN_4_INTR */
    DIN_SetInterruptMode(DIN_INTR_ALL, DIN_INTR_FALLING) ; 
    
    DIN_ClearInterrupt() ;
    isr_1_ClearPending() ;
    isr_1_StartEx(pin_isr) ;
}


int main(void)
{
    uint8_t intr_src=0 ;
    
    init_hardware() ;

    for(;;)
    {
        if (pin_intr_flag) {
            intr_src=pin_intr_src ;
            pin_intr_flag = 0 ;
            
            print("PIN ") ;
            
            if (intr_src & 0x01) { /* DIN_0 pushed */
                print("0 ") ;
            }
            if (intr_src & 0x02) { /* DIN_1 pushed */
                print("1 ") ;
            }
            if (intr_src & 0x04) { /* DIN_2 pushed */
                print("2 ") ;
            }
            if (intr_src & 0x08) { /* DIN_3 pushed */
                print("3 ") ;
            }
            if (intr_src & 0x10) { /* DIN_4 pushed */
                print("4 ") ;
            }
            
            print("pushed \n\r") ;
            CyDelay(20) ;
        }
    }
}

Tera Term log

001-TeraTerm-log.JPG

I hope this can be some hint for you.

moto

 

 

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RoRo_4659551
New Contributor II

I have already designed my PCB with pins connected to P5_0-P5_6, is there a way to use these pins?

 

Thanks,

Roy Roif

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MotooTanaka
Esteemed Contributor

Hi,

I think that if you change the pin assignment in Pins to fit your hardware,

above trick should work for you.

It was only I could not use P5[0] ~ P5[6] with my CY8CKIT-059.

moto

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Len_CONSULTRON
Honored Contributor II

Roy,

Maybe it is as simple as:

Len_CONSULTRON_0-1620129860803.png

This doesn't work on all PSOCs.  However it does work on the CY8CKIT_059.

It may not be as efficient as the port HW interrupt but this allows you to individualize ISRs.

Len
"Engineering is an Art. The Art of Compromise."
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RoRo_4659551
New Contributor II

ok I will try that, and which commands should i add for the interrupts?

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Len_CONSULTRON
Honored Contributor II

Roy,

It would be the exact same commands you were planning on using in your posted example.

For example:

CY_ISR(isr1)
{
/* Your ISR code here */
}
CY_ISR(isr2)
{
/* Your ISR code here */
}

main()
{
...
isr_1_StartEx(&isr1);
isr_2_StartEx(&isr2);
...
}
Len
"Engineering is an Art. The Art of Compromise."
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