PSoC 5LP SAR ADC delayes rising edge of input

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AnEy_1336741
Level 3
Level 3
10 replies posted 5 replies posted 5 questions asked

Hello everybody!

I found a strange behaviour of the SAR ADC in PSoC 5LP: I feed a GND-referred pulse over an opamp configured as a follower into a SAR ADC. The follower is in high power mode, the ADC in 12bit, 100kS/s and 0..Vdda with internal ref (2.5V) without bypass C. I can observe the input to the ADC at the ouput-pin of the opamp. As long, as the pulse keeps below 1V, everything is ok. When it starts to be higher, the ADC forces a delay of 1µs of the rising edge of the pulse. Despite there is the follower. The falling edge is ok. At all amplitudes of the pulse. Please find the attached pictures of the page in my project and of the oscilloscope screen (LabNation). The ADC_SAR2_in, which goes to another page, doesn't affect the delay. It's really the ADC. If I choose the bipolar ADC range 0..+-Vdda, everything is fine.

Any explanation?

Thanks!

Andreas

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1 Solution

Andreas,

I have reproduced your results and I have a root-cause for the issue.

In summary:  The issue is how you configured ADC_2 as an analog pin.

Len_CONSULTRON_0-1612823229089.png

In order to get the pin symbol as displayed above, you configured pin ADC_2 as Analog, Digital Input and Digital Output.   You probably also configured the Drive Mode to be Resistive pull-up/down.

Len_CONSULTRON_1-1612823321135.png

When I configure the pin in this manner I also get a 1us delay on the rising edge of a voltage exceeding the digital logic high threshold (~2.5V). 

If I change this pin to remove the Digital Input and Digital Output settings and use Drive mode High impedance analog (See pic below), my rise time is about 100ns consistently.  This is respectable for propagation delays due primarily to the Opamp.

Len_CONSULTRON_2-1612823459442.png

Len
"Engineering is an Art. The Art of Compromise."

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9 Replies
Len_CONSULTRON
Level 9
Level 9
Beta tester 500 solutions authored 1000 replies posted

Andreas,

What is the power setting of Opamp_2?

Len_CONSULTRON_0-1612614556050.png

 

Len
"Engineering is an Art. The Art of Compromise."
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Hello Len!

It is high power for sure and behaviour doesn't change with changing the power settings.

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odissey1
Level 9
Level 9
First comment on KBA 1000 replies posted 750 replies posted

AnEy,

With ADC sampling rate of 100kHz (10us/step) how much of importance 1 us delay?

/odissey1

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Hello odissey1!

1us delay is not a major problem. The problem is, that something happens, which I cannot understand. I want to know, which hurdles PSoC 5LP can put in my ways. Knowledge for future use. - The delay could bother the user, as he/she may want to observe the input channels (sig_n) via that way. And for the inputs a microsecond does play a role, since they are fed to a digital pulsewidth- and frequency-measurement-unit. And there is a microsecond a lot. Luckily, the digital path is ok.

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Len_CONSULTRON
Level 9
Level 9
Beta tester 500 solutions authored 1000 replies posted

Andreas,

I can't explain a 1us delay as you have detailed.  The analog path delays due to switch resistances, parasitic capacitances and Opamp_2 (@ high power) should be sub-nanosecond.

Assumption:  Your Amux_2 is constantly on your selected input channel.  If your Amux_2 is cycling between inputs this would account for input delays.

What is not known: You have an "off-page" connection labeled "ADC_2_in".   What is it connected to?   Is it possible that the down-stream circuit may be causing additional delays?

Len
"Engineering is an Art. The Art of Compromise."
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Hello Len, I checked everything. It's just disconnecting the ADC, which takes the delay away. The MUX is not cycling and I also disconnected the connection to the other sheet, to see if it changes anything. It does not. It is the ADC. And if I choose a 5V reference for the ADC instead of the 2.5V, the delay goes away. Unfortunately, I cannot use the 5V ref for unipolar operation.

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Andreas,

Interesting.   Good root-cause analysis.   Since we can get a peek inside the ADC_SAR, the next step is difficult.

I'm going to try to replicate your results.

Len
"Engineering is an Art. The Art of Compromise."
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Andreas,

I have reproduced your results and I have a root-cause for the issue.

In summary:  The issue is how you configured ADC_2 as an analog pin.

Len_CONSULTRON_0-1612823229089.png

In order to get the pin symbol as displayed above, you configured pin ADC_2 as Analog, Digital Input and Digital Output.   You probably also configured the Drive Mode to be Resistive pull-up/down.

Len_CONSULTRON_1-1612823321135.png

When I configure the pin in this manner I also get a 1us delay on the rising edge of a voltage exceeding the digital logic high threshold (~2.5V). 

If I change this pin to remove the Digital Input and Digital Output settings and use Drive mode High impedance analog (See pic below), my rise time is about 100ns consistently.  This is respectable for propagation delays due primarily to the Opamp.

Len_CONSULTRON_2-1612823459442.png

Len
"Engineering is an Art. The Art of Compromise."

Hello Len!

That's also strange, since I put the analog output pins into analog Hi Z mode via software. These two pins are, as four others, used for reading resistor coded switches at startup of the device. For this, a digital out and a digital in is needed. After that, I switch to hi Z:

// Get state of switches - Must be done before initializing everything else
/* Save the state of used pins <- Es gibt keine API dafür! Also nicht.
OpAmps are still off
Pins for S1 are set to strong output: CH1_out .. CH4_out (P15.3, P2.1, P1.2, P15.1)
Pins for S2 and S3 are set to Hi_Z: ADC_1, ADC_2 (P0.1, P3.7)
Set Pins to Resistive pull down (PIN_DM_RES_DWN)
Enable input functionality for these pins <- automatically done by choosing IO-drive-mode
Set threshould to LVTTL
Read pins, distribute results into mpm_hw_cfg
Disable input functionality <- automatically done by choosing IO-drive-mode
Set pins ADC_1 and ADC_2 to Hi_Z (PIN_DM_ALG_HIZ)
Set pins CH1_out .. CH4_out to strong (PIN_DM_STRONG)

Pinname Portpin Threshold-Ctrl-Reg Bit
CH1_out: P15.3 PRT15_CTL 0 (high=LVTTL, low=CMOS)
CH2_out: P2.1 PRT2_CTL 0 (high=LVTTL, low=CMOS)
CH3_out: P1.2 PRT1_CTL 0
CH4_out: P15.1 PRT15_CTL 0 (port wide!)
ADC_1: P0.1 PRT0_CTL 0
ADC_2: P3.7 PRT3_CTL 0

*/

void get_switches(void) {
CH1_out_SetDriveMode(PIN_DM_RES_DWN);
CH2_out_SetDriveMode(PIN_DM_RES_DWN);
CH3_out_SetDriveMode(PIN_DM_RES_DWN);
CH4_out_SetDriveMode(PIN_DM_RES_DWN);
ADC_1_SetDriveMode(PIN_DM_RES_DWN);
ADC_2_SetDriveMode(PIN_DM_RES_DWN);

ADC_1_Write(0);
ADC_2_Write(0);

// Enable input buffer <- automatically done by choosing IO-drive-mode
// Set threshold to LVTTL

CH1_out_CTL = CH1_out_CTL | 1;
CH2_out_CTL = CH2_out_CTL | 1;
CH3_out_CTL = CH3_out_CTL | 1;
CH4_out_CTL = CH4_out_CTL | 1;
ADC_1_CTL = ADC_1_CTL | 1;
ADC_2_CTL = ADC_2_CTL | 1;


mpm_hw_cfg.mpm_adress = CH4_out_Read()+CH3_out_Read()*2+CH2_out_Read()*4+CH1_out_Read()*8;
mpm_hw_cfg.mpm_switch2 = ADC_1_Read();
mpm_hw_cfg.mpm_switch3 = ADC_2_Read();

// Disable input buffer <- automatically done by choosing IO-drive-mode

ADC_1_SetDriveMode(PIN_DM_ALG_HIZ);
ADC_2_SetDriveMode(PIN_DM_ALG_HIZ);
CH1_out_SetDriveMode(PIN_DM_STRONG);
CH2_out_SetDriveMode(PIN_DM_STRONG);
CH3_out_SetDriveMode(PIN_DM_STRONG);
CH4_out_SetDriveMode(PIN_DM_STRONG);
}

I cannot remember, where I read that with writing the PIN_DM_ALG_HIZ, input buffers will also be deactivated. Seems as this is not the case. But I need a software solution for that. I will have to investigate further. Another thing is: Why does the delay disappear with choosing bipolar +-5V mode for the ADC?

Thank you!

Andreas

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