Can anyone help clarify my understanding of the I2S block? The advanced tab allows the number of channels to be set for both RX and TX. However simply setting RX to 4 channels chnages the block such that SDI is now marked up as sdi[1:0]. The console then warns that 'Terminal "I2S_1.sdi[1:0]" with width 2 is connected to "Net_105" with width 1.' with terminal and its connected wire do not have the same width.
Does this imply that a multichannel I2S block is effectively N stereo pairs in parallel rather than a true serial TDM mode?
FWIW I'm trying to establish if I can use one of these M0 or M3 parts to convert multi-channel serial audio to SPI.
Yes, multichannel means N pair of stereo channels. It is not serial time division multiplexed.
As far as I have come across with multichannel applications, codec's different channel ouputs (Front left, Front Right, Rear Left, Rear Right, Center etc) are connected to I2S different Tx pins. And similarly codec's different channel inputs are connected to I2S different Rx pins.
It is possible to convert these I2S data to SPI as a single serial data and send.
Would seem like chained DMA would be one approach, but bigger
question is what sample rate / channel are you going to need and how
many channels are you intending to use ?
Some DMA ref material -
http://www.cypress.com/?rID=37793 AN52705 Getting Started with DMA
http://www.cypress.com/?rID=82680 AN84810 PSoC® 3 and PSoC 5LP Advanced DMA Topics
http://www.cypress.com/?rID=44335 AN61102 PSoC® 3 and PSoC 5LP - ADC Data Buffering Using DMA
http://video.cypress.com/video-library/search/dma/ Videos on DMA
https://www.youtube.com/results?search_query=dma+psoc Videos on DMA (some overlap)
Thanks for the links. I will check these out.
The codec in question is a Cirrus CS42448, with 6 in and 8 outs. To make things simpler it is probably best to contemplate a 6In/6Out configuration. The preferred sample size would be 24bit at a rate of 48KHz. More than this would be a bonus.
Given the clarification re the I2S blocks, TDM is a red herring.
A better solution may be to use 3 I2S blocks driven from the common master clock, with the 3 SDI/SDO pins attached to the relevant DAC_SDIN and DAC_SDOUT pins on the codec. The clocking is common so the I2S SCK would drive ADC_SCLK and WS would drive the codec LRCK.
If this configuration works (and I've got the *absolute* basics taped up in PSOC Creator) then it will be a data issue. If the DMA unit can deliver the 3 channels to a single 32 bit aligned buffer then I'd have thought even the M0 core would be fast enough to push that onto the SPI bus (and handle incoming data at the same time)
It may be however that I've got this completely wrong and a CPLD/FPGA solution is better.