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PSoC 5, 3 & 1 MCU

New Contributor II

Hi,

I have faced a permenant onchip EEPROM damage on a certain byte two times in different units. The byte is stuck at FF no matter what, I tried reprogramming over EEPROM config tool etc. Why this may occur and how can I mitigate this problem?

Best,

Nico

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Honored Contributor

Nico,

Is it possible that your code is writing many times to the same EEPROM sector?   The PSoC5LP EEPROM has a write endurance of 1 million erase/program cycles @ 25C.

Additionally it is usually advisable to perform a CPU die temp operation (EEPROM_UpdateTemperature(void)) before writing to EEPROM.

Len

Len
"Engineering is an Art. The Art of Compromise."
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New Contributor II

Hi Len,

Thanks for the help. I wrote 5000 times when this error occurred. I do update temperature before writing to EEPROM as in the EEPROM examples.

Best,

Nico

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Honored Contributor

Nico,

5000 times is not enough to violate the write endurance specification.

Since this has happened on two separate boards to the same byte location, this is a issue for Cypress/Infineon to look into.

Maybe it qualifies for Field Failure analysis.

One more question:

What is the minimum voltage you are supplying to your PSoC?

Len

Len
"Engineering is an Art. The Art of Compromise."
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New Contributor II

Thanks Len,

How can I get in touch with Cypress support?

I use 5V voltage level and I supply 3V to one of the quadrants.

Best,

Nico

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Honored Contributor

Nico,

I was concerned if your supply voltage to VDDD for the EEPROM ever dropped below 1.71V.

If it did, it shouldn't destroy the EEPROM sector but it would corrupt it.

At this point, let's explore some "what if"s.

Thoughts:

Is it possible that you start the byte write with an erase but the actual programming to the intended byte value doesn't happen because of a reset?

For example, if you are running the Watchdog, did you pet it before starting the EEPROM change?

When the byte in question is 0xFF what are the values of the bytes in the same sector?

Len

Len
"Engineering is an Art. The Art of Compromise."
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Honored Contributor

Nico,

There are Cypress reps scanning all the forums.  I'm surprise one of them hasn't ventured a response by now.

Are you willing to share your project to see if someone else can reproduce the same issue?

If not, maybe this issue can be reproduced using test code.  Test code is almost always betters since it could be used as a benchmark/test suite for HW testing in the future.

Len

Len
"Engineering is an Art. The Art of Compromise."
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Moderator
Moderator

Hello Nico,

Can you please share your project.

We will try to reproduce the issue at our end.

Are you using a custom board to test this. In that case please provide schematic of the board for us to review.

What are the working condition under which the project is tested?

Best Regards

Ekta

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New Contributor II

Hi Ektan,

It's not possible for me to share the schematic and overall project as this is for a commercial application of my company.

It's a custom board.

Device is working under high humidity but we didn't measure.

Cheers,

Nico

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Honored Contributor

Nico,

How many CPUs has this EEPROM  damage occurred?

Knowing the general principles of EEPROM physics, there are only two conditions where an EEPROM cell would become permanently damaged:

  1. Exceeding the write endurance for the cell >1M.
  2. Writing the cell with voltage above the specified limit >5.25V

Since you indicated that the cell was written to about 5000 times, I'd say that 2. was more likely.

Len

Len
"Engineering is an Art. The Art of Compromise."
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