PSOC5LP Clock output creates power rail noise while "sweeping" through clock frequencies

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Anonymous
Not applicable

Hi all,

   

I am working on a project that requires me to output a variable frequency squarewave as an excitation signal and sample a sensor's response with an ADC.

   

I am currently using a 16bit SAR ADC to sample my signal.

   

I have also connected a clock output to a GPIO pin for my excitation signal.  To change the frequency, I send a command over UART which triggers the function:

   
​LCclock_SetDividerRegister(frequency,0);
   

Everything works as expected, however I see a bit of high frequency noise appear on my power rails, while "sweeping through frequencies" and this noise is carrying over into my analog circuitry.

   

Any ideas on how to fix this noise?  Maybe it is a grounding issue, or an issue with the PSOC5LP dev kit?  The noise level is much better when sampling only a single frequency.

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ETRO_SSN583
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Consider using polymer tantalums for bulk, they have a f vs z response ~ 1 order magnitude

   

better than conventional tants.

   

 

   

Carefully examine ceramic disk datasheets for their response over freq, not all .001, .01, .1's

   

are top performers. Also use of ferrite beads, again look at datasheets in detail.

   

 

   

Consider averaging, although that works best when noise uncorrelated.

   

 

   

https://www.dropbox.com/s/2h96beh1fbvz4e2/noise_notes.zip?dl=0

   

 

   

Regards, Dana.

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odissey1
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        Justin, To create variable frequency you may use DDS generator. Look at this eample of using variable frequency generator with lock-in detector: http://www.cypress.com/forum/psoc-5-device-programming/need-demo-program-lock-amplification And this example of DDS sweep generator http://www.cypress.com/forum/psoc-5-device-programming/generate-variable-frequency   
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ETRO_SSN583
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Or you  can use WaveDAC8 component to ge an excitation signal.

   

 

   

However whether you use DDS or WaveDAC8 you will get additional noise in the

   

supply rails. Keep in min d if using 16 bits, with a Vref of Vdd, the lsb is 76 uV.

   

If you use your scope on infinite persistence, look at supply rail, you will see a

   

couple hundred mV of noise, translate a couple K lsbs of noise. Very challenging

   

to do hi res A/D work.........

   

 

   

Regards, Dana.

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Anonymous
Not applicable

Thanks for the input, Dana! 

   

I believe the noise is most likely due to the PSOC5LP CY8CKIT-059 PCB design and I should be able to improve this on my own PCB.

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ETRO_SSN583
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Glad to help.

   

 

   

Regards, Dana.

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Anonymous
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Hi Oddysey1,

   

Thanks for the response, I think I must have missed it.  The DDS sweep generator you made is great!

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