PSOC5 PWM Maximum Usable Duty Cycle?

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Anonymous
Not applicable

I seem to be running into an issue, where I can't get my PWM to give me a real duty cycle above 90%, regardless of what I set the compare value to.  Am I doing something wrong or is this a limit of the device?

   

Device:CY8C5888AXI-LP096,

   

PWM Module: v 3.30, UDB mode, clocked with 64MHz Bus Clock

   

Can anyone help?

   

Thanks!

   

Scott

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Bob_Marlowe
Level 10
Level 10
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Welcome in the forum, Scott.

   

Have a look into the PWM's datasheet, DC specs say max frequency is 50MHz.

   

 

   

Bob

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HeLi_263931
Level 8
Level 8
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I'm pretty sure that the duty cycle can go up to 100%. This suggest that something in your project is wrong. maybe post it? (And explain how you measure the duty cycle)

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Bob_Marlowe
Level 10
Level 10
First like given 50 questions asked 10 questions asked

Welcome in the forum, Scott.

   

Have a look into the PWM's datasheet, DC specs say max frequency is 50MHz.

   

 

   

Bob

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Anonymous
Not applicable

Thanks, that was it.  Actually, I'm using 16-bit, one output, so that makes the max frequency 43MHz per the data sheet.

   

Interestingly though, I'm out of clocks, having used the UART, SPI, all 3 ADC's, couple of counters.  So, I tried to manually clock the two SAR's, so they'll free the slot I needed for the new 43MHz clock.  When I do that, the closest I can get to 18MHz is 16MHz for the SAR's, and the 43MHz says it's 63MHz still. I've just got too much going on in here?

   

Scott

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Bob_Marlowe
Level 10
Level 10
First like given 50 questions asked 10 questions asked

Each clock is derived by IMO and the PLL and a division by an integer number. So when you set PLL frequency to 80MHz you can get as close as 40MHz by a division by 2. Or you set the PLL directly to 42MHz.

   

 

   

Bob