Dear all PSoC enthusiasts friends.
I am having a little struggle in developing a system that Integrates a HDL part along with a MCU part. Basically the system will work as a PLC in which all the communication (SPI, GPRS - UART, Zigbee - UART, i2c and DAC) will be handled by the Cortex-M3 of the PSoC 5LP. Therefore the logical part of the design, in which I will be setting and reading digital ports, I want to use the PLD capability of the PSoC architecture.
I have already made a project in which I use several Status Register and Control Register blocks along with my Verilog component and it has worked quite well so far. The struggle is that I only have 24 of each Register block. I tried to find a way of accessing (read or write) registers mapped on RAM via Verilog, but I could not find a way of doing that. Do you have already worked with something like that? How could I pass information between the MCU and the PLD part of the design without using Control and Status Registers?
Thank you very much
Been reading all of the TRM and other literature and I don't think it's possible - see section 23.3.3. of the PSOC5 TRM. I don't think you can pass information to/from PLD without writing/reading control/status registers as the system bus connects to them, but not directly to the PLD fabric. The status and control appear to provide the connection between the system bus and the routing channel for PLD as far as I can see, but one of the experts may know of a way otherwise.
You can easily access the registers of your verilog components from CPU in C-language. There have been names generated for the registers. Look at "Component Author Guide" chapter 6.4 Completing the .h File.
Now for the bad news: You cannot access ram (or flash) from a verilog component. There are provisions to use DMA, but no chance of retrieving or storing data directly from UDB to SRam.
Dear Bob Marlowe and bosleymusic.com,
Thank you for your replies. I was afraid it was only possible via Status and Control registers. I will read a little more if I can use the datapath FIFOs as a way to access data to and from the PLD as Bob has indicated in the chapter 6.4. I understood that I can map all datapaths registers into the .h file and then access it in C-language (correct me if I am wrong), thus I pan to use the FIFO to store the values and then retrieve it one by one in the Verilog code. The issue is that I have 10 Analog Channels of 16 bit each plus all the digital interfaces to work between the PLD and the MCU.
You are getting near the chip limits: 10 channels to be handled width 16bits might cost you 20 UDBs!
Can you specify what exactly you want to do?
The project I am working on is basically a embedded PLC with GPRS and XBEE communication. I have several other smaller boards that use a PSoC 4 chip that reads a string of digital temperature sensors and send the package containing the battery status + Packet Identification + Sensors data via Zigbee Protocol to the Main Board (Embedded PLC). This main board receives all the information from all the nodes, handle the data, handle the operational logic (Verilog - Controling digital IOs) and also have 10 Analogic channels that are configured to operate in industrial standards (0-10V, 0-12V & 4-20mA). It also has the ability to pack all information regarding the nodes data + IOs states + Analog values and send it to a remote server via GPRS communication using an serial based Cellular module.
It is currently under development. I know that I might need to use more external circuitry to free the PSoC 5 such as ADs and possibly an PLD to handle the logic operation.
Do you have any suggestion for improving the project?