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PSoC 5, 3 & 1 MCU

New Contributor II

Hi,

   

Using a PGA to buffer a small signal before input to a mux and ATD. The part is configured to use Internal Vss.

   

In the program, I accidently forgot to turn it on via PGA_Start() yet it does give me a directly proportional output with a range that is repeatable and can be calibrated. If the part is turned on, then the dynamic range is reduced to an unusable range, though the ATD count is much higher.

   

Is the part actually in a low power state and receiving power if I fail to do a PGA_Start()?

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Esteemed Contributor

I set up attached test bed.

   

 

   

With PGA off, 10 Khz in, G = 1 or 50, I measured 100 mV out of feedthru.

   

 

   

My guess is that when PGA is off the feedthru occurs thru stray C of fdbk network,

   

which is probably not switched open when PGA is off ? Note I used adjacent pins so

   

that could contribute to pin to pin coupling. So I moved output to end of port pins

   

and feedthru dropped to 50 mV.

   

 

   

Regards, Dana.

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Esteemed Contributor

If you are taking G with a PGA then your CM input range is reduced by

   

the G you are using before you drive the output into distortion/saturation.

   

So if you used G = 10, on a Vdd of 5, then input range is limited to 0 - .5

   

before you loose CM range on the output.

   

 

   

Not sure of effect you are seeing before its started, what freq are you

   

inputing to PGA. When you start it if power up in with the G and Power

   

level as configed, unless you use APIs to change them.

   

 

   

Regards, Dana.

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New Contributor II

I'm trying to find out if the PGA is getting power without issuing a PGA_Start(). It might be a question for a semiconductor / VHDL guru.

   

If there is no power applied to the PGA, then I'm doing something like driving a diode through the feedback resistors. The signal is basically a DC level around 240mV.

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Esteemed Contributor

You have a schematic and scope capture of in and out ?

   

 

   

Regards, Dana.

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New Contributor II

No scope capture, just reading the ADC_DelSig counts. The input is straight DC, typically 240 millivolts. The PGA is in place to boost a photo diode output.

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New Contributor II

Attached as document.

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Esteemed Contributor

I set up attached test bed.

   

 

   

With PGA off, 10 Khz in, G = 1 or 50, I measured 100 mV out of feedthru.

   

 

   

My guess is that when PGA is off the feedthru occurs thru stray C of fdbk network,

   

which is probably not switched open when PGA is off ? Note I used adjacent pins so

   

that could contribute to pin to pin coupling. So I moved output to end of port pins

   

and feedthru dropped to 50 mV.

   

 

   

Regards, Dana.

View solution in original post

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New Contributor II

Thank you for trying that, Dana. I've subsequently opened a case to see what they say and the initial response was that the SC/CT block is configured at boot up, which incorporates capacitors. I'll report back what I hear from them.

New Contributor II

So I did open a case and they sent me a project that routes the PGA output to a pin. Their result was a fluctuating voltage due to "a high Z condition. Not sure what the goal of trying the project is yet. I guess so that I can see a fluctuating voltage on a scope in a configuration I'm not using? I did read the PSoC3 architecture section that talks about Miller capacitance. Surely there is someone that understands what's happening at the silicon level.

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Esteemed Contributor

Looking at attached, SC/CT Block from which PGAs are made of, you can see

   

quite a few opportunities for feed thru, off switch parasitics, etc.. This of course

   

does not address silicon issues, like source bulk effect currents modulating

   

driver thresholds, etc.. although I think good design and isolation would have

   

addressed most of this. I would have to file a CASE but I thought that when

   

a _Stop() was issued to a CT block all bias networks were turned off, eg. the

   

block is no longer active. Otherwise how could they achive the deep sleep current

   

specs.....

   

 

   

That was a great project they sent you....:)

   

 

   

Are you using, in addition to PGA, a TIA to condition the photodiode ? You can

   

take a lot of conversion G there properly setup.

   

 

   

Regards, Dana.

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New Contributor II

The thing is, I didn't issue the PGA_Stop(). I just powered up and started the reading the output in the ADC_DelSig, so there might be an encounter of the third kind, ha ha,.

   

Your suggestion about the TIA sounds like the right idea and is what we may be trying next but with an available external op-amp. My problem was, in measuring the light, I was only getting about a 10 ADC count range from fully on to all the way off. The ADC is set to 16 bit and the readings were in up around 10,000. I put in the PGA and it gave me a repeatable range of around 400 counts, which allowed me to calibrate but it was in the range of 700 - 1100 counts. If I hear anything back on my case I'll drop it in here.

   

Thanks for your help.

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Esteemed Contributor

Basically you are working with photo diode currents which are small. But the TIA

   

has a conversion G quite high since the Rfb can be in the M Ohm range. Just try

   

it.

   

 

   

https://www.google.com/url?sa=t&rct=j&q=&esrc=s&source=web&cd=1&ved=0CB4QFjAAahUKEwj9pc3l9J_IAhXPth4...

   

 

   

Regards, Dana.

New Contributor II

Hi Dana,

   

I did try it and the TIA is definitely the solution but I also put in a PGA_INV so the counts I'm reading are in phase. The downside is the amplification also amplifies the noise level but we'll deal with that next. Appreciate your looking into this and guidance. It has indeed been a help.

   

Nick

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