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PSoC 5, 3 & 1 MCU

mfuji
New Contributor

I found out some outlier values read from Quadrature Decoder module. Could you help us to solve this issue ?
I'd like to confirm the limitations of the Quadrature Decoder settings and I'd like to know other more convenient module to resolve this issue.

- Part number
PSoC5 (CY8C5888LTI-LP097)

- Usage of Quadrature Decoder
Counter of BLDC motor's encoder

- How to check
1. Drive motor at constant velocity (10000rpm, 2000pulse/rev -> 333kpulse/s)
2. Read counter value by using ENC_COUNTER_GetCounter(). This function called by Timer IRQ (generated by Counter module, 5kHz) *:ENC_COUNTER is the name of Quadrature Decoder
3. At constant velocity, counter value increased/decreased constantly. But sometimes, outlier value can be read. The value is 2^15 pulses higher than the value estimated by the velocity.

- Settings of  Quadrature Decoder
 CLOCK: 11.8MHz (BUS_CLK: 59MHz)
 Counter size: 32bit
 Counter resolution: 4x
 User Index: Disable
 Glitch filtering: Disable

 

I checked the auto-generated sources of PSoC Creator 4.3 and I found some part of "Quadrature Decoder" is implemented by the software. "ENC_COUNTER_count32SoftPart" is updated by "ENC_COUNTER_ISR ".
I think it may be better not to use "Quadrature Decoder" with 32bit because it is possible to prevent ENC_COUNTER_ISR  by "CyIntDisable". ENC_COUNTER_count32SoftPart may not be updated by the latest real count.
Just I'd like to count the 2-phase pulses. How should I configurate it ? Do you have any other modules I can use ?

ENC_COUNTER.c
int32 ENC_COUNTER_GetCounter(void)
{
    ......
    CyIntDisable(ENC_COUNTER_ISR_NUMBER);
    tmpCnt = ENC_COUNTER_Cnt16_ReadCounter();
    hwCount = (int16) ((int32) tmpCnt - (int32) ENC_COUNTER_COUNTER_INIT_VALUE);
    count = ENC_COUNTER_count32SoftPart + hwCount;
    CyIntEnable(ENC_COUNTER_ISR_NUMBER);
    ......
}

ENC_COUNTER_INT.c
CY_ISR( ENC_COUNTER_ISR )
{
    ......
    if (0u != (ENC_COUNTER_swStatus & ENC_COUNTER_COUNTER_OVERFLOW))
    {
        ENC_COUNTER_count32SoftPart += (int32) ENC_COUNTER_COUNTER_MAX_VALUE;
    }
    else if (0u != (ENC_COUNTER_swStatus & ENC_COUNTER_COUNTER_UNDERFLOW))
    {
        ENC_COUNTER_count32SoftPart -= (int32) ENC_COUNTER_COUNTER_INIT_VALUE;
    }
    ......
}

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1 Solution
Vasanth
Moderator
Moderator

Hi,

Are you using interrupt disable in your code. If yes this is expected. The 32-bit counter implements the lower 16 bits in the hardware counter and the upper 16 bits in software to reduce hardware resource use. For this target, an additional ISR is used. To work properly with the 32-bit counter, interrupts must be enabled.

There is no other quadrature component available in PSoC5 device. I have attached a previous thread with an example code, which may be helpful to you. 

Best Regards,
Vasanth 

View solution in original post

3 Replies
Vasanth
Moderator
Moderator

Hi,

Are you using interrupt disable in your code. If yes this is expected. The 32-bit counter implements the lower 16 bits in the hardware counter and the upper 16 bits in software to reduce hardware resource use. For this target, an additional ISR is used. To work properly with the 32-bit counter, interrupts must be enabled.

There is no other quadrature component available in PSoC5 device. I have attached a previous thread with an example code, which may be helpful to you. 

Best Regards,
Vasanth 

View solution in original post

mfuji
New Contributor

Hi Vasanth.

Thanks your support.

In my project, interrupt is enabled but the priority of Quadrature Decoder is lower than the others. This means that the interrupt of Quadrature Decoder may be blocked. I understand it.

I found that if  Quadrature Decoder is configurated as 16bit counter, there is no interrupt function for Quadrature Decoder.

As you mentioned, is Quadrature Decoder configurated as 16bit counter implemented in the hardware ? and does it be expected not to read the outlier values ?

In my system, the counter is monitored periodically and even if the counter is overflowed, the count value may be calculated.

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Vasanth
Moderator
Moderator

Hi, 

Yes, your understanding is right. In 32 bit mode only the ISR is used. In case the you are using 16 bit counter, then as it purely on hardware ISR part is not needed. If that meets your application requirement, you can use it in 16 bit mode.

Best Regards,
Vasanth

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