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PSoC 5, 3 & 1 MCU

AlVa_264671
New Contributor II

Hi There

Maybe someone can help me to optomize the attacched project.

Thank you very much in advance.

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1 Solution
Anonymous
Not applicable

Hi,

Attached the modified project. I have selected specific pins and net constraint for successful routing. If you notice in the analog viewer in .cydwr, positive input of DelSig ADC connects to all the analog global left (AGL) lines, but negative input connects to only odd numbered lines. But in the design, you want pins to be able to connect to both input ends of the ADC (on consecutive AMUX channels). So, the pins that can connect to odd numbered AGL lines are selected.

pastedImage_0.png

Another way was to configure the AMUX and ADC in single ended mode and get the differential voltage in firmware.

-Rajiv

View solution in original post

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3 Replies
Anonymous
Not applicable

Hi,

Attached the modified project. I have selected specific pins and net constraint for successful routing. If you notice in the analog viewer in .cydwr, positive input of DelSig ADC connects to all the analog global left (AGL) lines, but negative input connects to only odd numbered lines. But in the design, you want pins to be able to connect to both input ends of the ADC (on consecutive AMUX channels). So, the pins that can connect to odd numbered AGL lines are selected.

pastedImage_0.png

Another way was to configure the AMUX and ADC in single ended mode and get the differential voltage in firmware.

-Rajiv

View solution in original post

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AlVa_264671
New Contributor II

Hi Rajiv

You are a great help for me.

I was trying keep all pins contiguous.

Thank you so much.

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Anonymous
Not applicable

you're welcome

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