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Does this device have input voltage ripple or spike regulations?
Ripple will occur up to 130mVp-p at 5V in low temperature conditions. LVD is set to 4.81V(Typ), but it has not been reset. (VM[2: 0] = 111b)
Thanks,
Tetsuo
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PSoC1 MCU
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Hello Tetsuo-san,
This device does not have power supply voltage ripple specifications or power supply spike specifications. However, the power supply voltage on VDD must be maintained within the operating voltage range to ensure proper intended operation. The ranges are 4.75V to 5.25V and 3.00V to 3.60V.
Under the conditions that you have let us know, LVD does not trip, since the VDD has not gone below 4.81V. Assuming the nominal voltage of the power supply is 5V, a 130mVp-p ripple will cause VDD to drop to 5V - (130mV/2) ~= 4.935V, which is above the LVD threshold.
Do kindly refer to Power supply ripple effect on internal reference of PSoC 1 for some more information on the effects of ripple.
Best regards,
Sampath Selvaraj
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Sampath-san,
Thank you for your answer. I can understand about device spec.
Is it possible for PSoC to internally generate ripples in the power supply? (e.g. change in capacitance, GND bounce, ...)
Currently, the cause of the large input voltage ripple at low temperatures is still unknown. I'm checking both internal and external factors of PSoC.
Thanks,
Tetsuo
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Hello Tetsuo-san,
It is possible for PSoC to internally generate ripples, by turning on and off various peripherals, or turning on and off GPIOs sinking or sourcing large currents. If these are within the specifications, they will not affect the normal operation.
Do kindly let me know your actual observation, so that I may understand the issue better.
Best regards,
Sampath Selvaraj
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Hello Tetsuo-san,
Is it possible to repeat the above measurement with the bypass capacitors on the VDD of CY8C24894-24LTXI removed?
Best regards,
Sampath Selvaraj