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I have executed the following function to initialize the I2C slave device, but it seems that communication is not working properly.
I2CMAST_MasterClearStatus();
Stat = I2CMAST_MasterWriteBuf(AQM0802_ADW, &TestData, 2, I2CMAST_MODE_COMPLETE_XFER);
for(;;) {
if(0u != (I2CMAST_MasterStatus() & I2CMAST_MSTAT_WR_CMPLT))
break;
}
※Note Slave Address:0x7c、The contents of TestData are 0x80,0x34
Additional information:Implementation is a fixed function
The actual waveform as a result of executing the WriteBuf function is (See attached document)
It seems that only the first slave address is transferred from the actual waveform
There seems to be no problem with the transfer timing of the slave address.
I would appreciate any good advice on this phenomenon.
Thank you
Solved! Go to Solution.
- Labels:
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PSoC 3
-
PSoC 3 Device Programming
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Hi,
Can you please follow the following firmware flow and try once?
(void) I2CM_I2CMasterClearStatus();
/* Start I2C write and check status*/
if(I2CM_I2C_MSTR_NO_ERROR == I2CM_I2CMasterWriteBuf(I2C_SLAVE_ADDR,
buffer, PACKET_SIZE,
I2CM_I2C_MODE_COMPLETE_XFER))
{
/*If I2C write started without errors,
/ wait until I2C Master completes write transfer
*/
while (0u == (I2CM_I2CMasterStatus() & I2CM_I2C_MSTAT_WR_CMPLT))
{
/* Wait */
}
/* Display transfer status */
if (0u == (I2CM_I2CMasterStatus() & I2CM_I2C_MSTAT_ERR_XFER))
{
/* Check if all bytes was written */
if (I2CM_I2CMasterGetWriteBufSize() == BUFFER_SIZE)
{
status = TRANSFER_CMPLT;
}
}
}
The above firmware flow is taken from the Cypress code example on SCB based I2C Master. I am attaching the code example for your reference. Please test it at your side and update us.
Thanks
Ganesh