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PSoC 5, 3 & 1 MCU

timoc_264486
New Contributor II

According to the datasheet for a 16-bit UDB timer the maximum clock frequency is 33 MHz. When I set the clock input to 33 MHz (or anything greater than 24 MHz for that matter) I get the following warning:

Ashampoo_Snap_Monday, April 1, 2019_09h30m59s_002_.png

If the datasheet is correct, why does it mention 24 MHz? Is my timer being clocked at 33 MHz even though I am getting this warning?

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timoc_264486
New Contributor II

After some experimentation, I tested this and it seems to work:

1. Set the temperature range on the System tab of the .cydwr file to:

Ashampoo_Snap_Tuesday, April 2, 2019_11h28m40s_009_.png

This boosted the maximum bus clock to slightly over 53 MHZ per the System Timing Analysis.

2. Set the system clocks to this:

Ashampoo_Snap_Tuesday, April 2, 2019_11h32m42s_011_.png

3. Setup the timer like this:

Ashampoo_Snap_Tuesday, April 2, 2019_11h36m52s_012_Configure -Phase-Timer-.png

I get decent resolution when using the rising edge of Trigger which counts down until the rising edge of capture. I wait for the Capture bit = true in the status register then read the value in Capture register. I then divide that value accordingly and multiply by 360 to get the phase shift in degrees. Pretty nifty. You would need adjust things according to the cycle of the signals you are measuring and the range phase angle you are expecting to measure.

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Vison_Zhang
Moderator
Moderator

That's because internal MASTER_CLK is configured to 24MHz,  not 33 MHZ or 33*N MHz. So internal clock divider cannot divide a 33MHz clock for Timer component, it can only provide a 24MHz clock.

Change MASTER_CLK to 33MHz or 66MHz can fix this issue.Capture.JPG

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timoc_264486
New Contributor II

I have done a lot of development with Creator but I haven't spent any time with the clocks so thank you for this pointer. This gets me closer but now STA is telling me there is a setup timing violation:

Ashampoo_Snap_Tuesday, April 2, 2019_08h50m06s_003_.png

I am also seeing what appears to be the result of the violation in the form of a hang when reading the timer status register. I like the 66 MHz resolution I am seeing in the capture timing of the counter and would like to figure out how to keep it but don't know what affects the 39.339 MHz number and whether I have any ability to increase it. Anyone know?

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timoc_264486
New Contributor II

BTW - I switched back to an 8 bit timer since it had all of the resolution I needed. So in theory I should be able to run up to 44 MHz -- except that I am using a trigger and there is no timing supplied for that configuration. I may try to sync my inputs and used a fixed function timer which per the spec sheet can run at up to 80 MHz. I tried that before but Enable requires setup and hold time which my asynchronous inputs could not be guaranteed to meet and so I was also seeing hangs in that configuration. Hopefully if I sync the inputs that should go away. I'll lose some resolution but might gain it back with the higher timer clock speed.

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timoc_264486
New Contributor II

After some experimentation, I tested this and it seems to work:

1. Set the temperature range on the System tab of the .cydwr file to:

Ashampoo_Snap_Tuesday, April 2, 2019_11h28m40s_009_.png

This boosted the maximum bus clock to slightly over 53 MHZ per the System Timing Analysis.

2. Set the system clocks to this:

Ashampoo_Snap_Tuesday, April 2, 2019_11h32m42s_011_.png

3. Setup the timer like this:

Ashampoo_Snap_Tuesday, April 2, 2019_11h36m52s_012_Configure -Phase-Timer-.png

I get decent resolution when using the rising edge of Trigger which counts down until the rising edge of capture. I wait for the Capture bit = true in the status register then read the value in Capture register. I then divide that value accordingly and multiply by 360 to get the phase shift in degrees. Pretty nifty. You would need adjust things according to the cycle of the signals you are measuring and the range phase angle you are expecting to measure.

View solution in original post

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