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I am using the CY8CMBR3116 in a design. The farthest three buttons are being automatically turned off due to high parasitic capacitance. Their values are as follows:
CS1 DEBUG_CP: 46
CS11 DEBUG_CP: 46
CS12 DEBUG_CP: 49
I do not believe this number should be so high. My design is four layers, round sensor shapes with 16mm diameter, top layer is a 45mil hatched shield, layer two is 70mil hatched ground and sensor traces, layer 3 is 70mil hatched ground, bottom layer is 70mil hatched ground and CapSense controller. No other traces run over my sensor traces, and the clearance around the sensor traces to hatched ground is 7 mil. Traces are 7mil. Trace lengths are: 114mm for CS12, 91mm for CS11 and 113mm for CS1.
My current plan to lower parasitic capacitance is:
-increase the clearance around the sensor traces from 7mil to 20mil
-possibly remove layer 2 and layer 3 hatched grounds
I want to lower the parasitic capacitance so that I am able to use auto-tuning (pF <= 45). Is anything standing out that I can change in hardware or software that will help lower the parasitic capacitance? Thanks!
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- capsense
- cy8cmbr3116
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Hello,
Yes, the recommended button-ground clearance should be a minimum of 0.5 mm (20 mil).
You can also connect the layer 2 hatch to shield instead of ground. This would reduce Cp.
Also, is it necessary to have 16 mm diameter buttons? What is the overlay material and thickness used?
You can refer to MBR 3xxx CapSense design (Design toolbox) to decide on the sensor dimensions.
Unfortunately, there is no change that can be done in software.
Thanks,Shanmathi