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AFAIK you can only instantiate components that are itself defined in verilog. So look whether the one you need is (there must be a meaningful .v file).
You need to include this .v file into yours (or cypress.v if its a PSoC building block such as clocks or control regs) and then just instantiate the component. I did a quick search in the existing components, and many of them instatiate registers and clock blocks - but I did not find one the re-uses another component. But looking at them should show how its done.