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PSoC 5, 3 & 1 MCU

joeac_1591236
New Contributor II

I am trying to measure the roughly 50% duty cycle of a 750kHz free running signal.  I am using the UDB implementation of the Timer block with a 24MHz input clock with a rising edge trigger mode and a software controlled capture mode (which I set to falling edge).  I would like to record the number of clock cycles ("time") between rising and falling edge of the signal and to take numerous measurements in order to average the result.

How do I do this?

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joeac_1591236
New Contributor II

Hi ScottA_91​,

Since I read that the UDB counter can only accept a count frequency less than or equal to half the clock frequency, I moved back to the timer block and worked this out as a solution.  The Capture_Out will set the SR latch to hold the Timer reset high, giving me all the time I need to record the value from the capture FIFO.  Then I manually reset the latch once I've finished recording the value and the timer will then start to trigger on the next rising edge of the signal and stop again on the captured falling edge. 

Thanks for your help.

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ScottA_91
Employee

Well if it was me, I'd setup things a little differently.

Create a 32-bit counter (UDB) and setup enable to be a hardware signal.  Connect the input signal to this enable.  Make it an up counter.  Run the 24MHz clock in, and set the pin to interrupt on falling edge.

When the interrupt is triggered, clear it and set a flag for your main loop.

In you main loop, if the flag is set, copy out the new 32 bit value, and reset the counter.  Then average your values.

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joeac_1591236
New Contributor II

I see the merits of that solution and was able to do a proof-of-concept with a slight variation from your suggestion.  However, I am now running into a timing issue.  Ideally, I want clock and count to be the same to achieve the highest resolution but I'm unable to capture data when running the 24MHz clock to both count and clock due to an asynchronous routing issue.  I am able to read data when I put an 8MHz clock on the count pin.

Do you have any recommendations for how to get the count and clock to run at 24MHz?  See my test project attached.

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joeac_1591236
New Contributor II

Hi ScottA_91​,

Since I read that the UDB counter can only accept a count frequency less than or equal to half the clock frequency, I moved back to the timer block and worked this out as a solution.  The Capture_Out will set the SR latch to hold the Timer reset high, giving me all the time I need to record the value from the capture FIFO.  Then I manually reset the latch once I've finished recording the value and the timer will then start to trigger on the next rising edge of the signal and stop again on the captured falling edge. 

Thanks for your help.

pastedImage_0.png

View solution in original post

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