Strictly necessary cookies are on by default and cannot be turned off. Functional, Performance and Tracking/targeting/sharing cookies can be turned on below based on your preferences (this banner will remain available for you to accept cookies). You may change your cookie settings by deleting cookies from your browser. Then this banner will appear again. You can learn more details about cookies HERE.
Strictly necessary (always on)
Functional, Performance and Tracking/targeting/sharing (default off)
I need a 3mbps UART, but I also want to run my PSoC5 at 64MHz. This creates a conflict, because a 3mbps UART needs either a 24MHz or a 48MHz clock, and so I can't use a 64MHz master clock. (It's a shame I can't get access to the 48MHz USB clock).
One way around this would be to create a 4/3 or 8/3 clock divider. I've looked online, but can't find any examples of how to do this. Does anyone know if it's possible to do such a thing in Verilog?
You can get 3MHz from 64MHz bus_clock using DDS32 module http://www.cypress.com/comment/405656#comment-405656 Whether it will work as a clock for UART, that is the question, because of the jitter produced at high frequency. Then next option is custom PLL, which is also doable by PSoC.