Jun 15, 2017
02:48 AM
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Jun 15, 2017
02:48 AM
I need a 3mbps UART, but I also want to run my PSoC5 at 64MHz. This creates a conflict, because a 3mbps UART needs either a 24MHz or a 48MHz clock, and so I can't use a 64MHz master clock. (It's a shame I can't get access to the 48MHz USB clock).
One way around this would be to create a 4/3 or 8/3 clock divider. I've looked online, but can't find any examples of how to do this. Does anyone know if it's possible to do such a thing in Verilog?
Many thanks - Hugo
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PSoC 5LP
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Jun 15, 2017
09:13 AM
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Jun 15, 2017
09:13 AM
You can get 3MHz from 64MHz bus_clock using DDS32 module http://www.cypress.com/comment/405656#comment-405656 Whether it will work as a clock for UART, that is the question, because of the jitter produced at high frequency. Then next option is custom PLL, which is also doable by PSoC.
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Jun 15, 2017
09:13 AM
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Jun 15, 2017
09:13 AM
You can get 3MHz from 64MHz bus_clock using DDS32 module http://www.cypress.com/comment/405656#comment-405656 Whether it will work as a clock for UART, that is the question, because of the jitter produced at high frequency. Then next option is custom PLL, which is also doable by PSoC.