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PSoC 5, 3 & 1 MCU

New Contributor

I would like to increase the SAMPLEwidth (as it is named in the datasheet) in the Sequencing SAR ADC component. Currently I'm using the following configuration:

pastedImage_0.png

This sampling rate is giving me a lot of crosstalk between channels and i'm trying to address it by modifiying some resistors and capacitors in order to charge the S/H circuit faster. I would like to be able to change the SAMPLEwidth (6 clock cycles by default) as well to see the impact on the results.

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Moderator
Moderator

Hi Manuel,

Kindly check the registers TRM. The register SAR_SAMPLE_TIME01 can be modified to adjust the sample time as you need.


Best Regards,
Vasanth R S

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6 Replies
Moderator
Moderator

Hi Manuel,

I could not understand what exactly is the parameter you are looking for ? I could not find SAMPLEwidth parameter as you have defined in the datasheet. Are you interested in sampling time ? Are you interested in increasing the acquisition time ?

Best Regards,

Vasanth

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New Contributor

Hi Vansanth,

Looking at the functional description of the sequencing SAR ADC:

"Converting one sample in free running sample mode takes 12+6 clock cycles, or 12+4 clock cycles if Reference is Internal Vref (not bypassed), where 12 is a resolution in bits (RESOLUTIONbits), 6 (or 4) is a sample width and auto-zeroing (SAMPLEwidth)."

I guess this value (SAMPLEwidth) sets the number of clock cycles to charge the S/H circuit, since the autogenerated code of the component has a macro like this (in ADC_HF_SAR.h, ADC_HF is the component's name):

/* Number of additional clocks for sampling data*/

#define ADC_HF_SAR_SAMPLE_PRECHARGE       (6u)

This value matches the information in the datasheet, and I thinks it's took from the ADC_SAR_SEQ_v2_10.cysym, under symbol parameters (SamplePrecharge):

pastedImage_0.png

As you can see, this value is 4 or 6 depending on the reference and range. In fact, I'm using the second ADC of PSOC5 with the next configuration:

pastedImage_1.png

And in this case, the macro is set as follows:

/* Number of additional clocks for sampling data*/

#define ADC_LF_SAMPLE_PRECHARGE       (4u)

Given this information, I guess that 4 or 6 are the clock cycles used to charge the S/H circuit before performing the 12 bit conversion.

Am I understanding this correctly?

I would like to modify this value in order to reduce crosstalk between channels without reducing the sampling rate to much.

I have already tried to create a new component based on the ADC_SAR_SEQ modifying the SamplePrecharge in the symbol parameters of ADC_SAR_SEQ_v2_10.cysym, renaming the component's name and updating the namespaces used in all *.cs files.

The component appears in the catalog and the sampling times are calculated correctly in the configuration window, but i'm not able to compile the project, it gets stuck at clening up... and the sources are generated very slowly.

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Moderator
Moderator

Hi Manuel,

Kindly check the registers TRM. The register SAR_SAMPLE_TIME01 can be modified to adjust the sample time as you need.


Best Regards,
Vasanth R S

View solution in original post

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New Contributor

1.3.407 SAR[0..1]_CSR2 SAR status and control register 2

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Honored Contributor

user_3159566,

You're trying to do so very advanced things by trying to tune the SAR_ADC internal operations.  I wish you luck on that.

Is it possible the crosstalk you're seeing is less complicated of a root cause?  For example do you have an AMux in front of the SAR_ADC?

If so, the Amux can be prone to crosstalk depending on your isolation settings.  Even if you get the Amux isolation to be maximum, you would need to make sure the SAR_ADC conversion is started AFTER the AMux switch is completed.

Just some thoughts.  Good luck!

Len

Len
"Engineering is an Art. The Art of Compromise."
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New Contributor

Hi LePo_1062026,

Thank you for your analysis.

In this particular case, I'm using the sequencing SAR ADC, which uses an AMUX, but I don't control it directly.

Using the second ADC and a sequencing AMUX I can see crosstalk even after waiting a few milliseconds between switching the AMUX and triggering the ADC conversion.

I will try to find a moment to make an example porject that shows the problem.

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