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Hi,
If I write a 16 bit full adder in verilog it will be something like
assign { cout, S } = { 1'b0, A } + { 1'b0, B } + { 4'd0, cin } ;
Since I don't have access to my 5LP boards today, following is an idea sketch.
I'm assuming a CY8CKIT-059 for the target board.
Symbol for the verilog full adder
Verilog
Schematic
main.c
=================
#include "project.h"
#include "stdio.h"
#include "tty_utils.h"
void init_hardware(void)
{
CyGlobalIntEnable; /* Enable global interrupts. */
tty_init() ;
}
int main(void)
{
uint16_t a, b, s ;
int cin, cout ;
init_hardware() ;
splash("UDB 16bit Full addder test") ;
print("Enter A B cin\n") ;
prompt() ;
for(;;)
{
if (get_line()) {
sscanf(str, "%hd %hd %d", &a, &b, &cin) ;
A_LSB_Write( a & 0xFF ) ;
A_MSB_Write((a >> 😎 & 0xFF) ;
B_LSB_Write( b & 0xFF ) ;
B_MSB_Write((b >> 😎 & 0xFF) ;
cin_Write(cin) ;
s = (S_MSB_Read() << 😎 | S_LSB_Read() ;
cout = cout_Read() ;
snprintf(str, STR_BUF_LEN, "%d + %d + %d = ", a, b, cin ) ;
print(str) ;
snprintf(str, STR_BUF_LEN, "%d (cout = %d)\n", s, cout) ;
print(str) ;
prompt() ;
}
}
}
=================
So the good news is that at least this project is build-able,
but the bad news is that I have not tried it by myself.
Your mileage may vary 😉
moto
P.S. On 4-Nov-2019, I had a chance to test the project with CY8CKIT-059
Although I could not afford time to test all patterns, the samples I entered seem to be fine.
NOTE: I even managed to write "addder" for the title to fulfill the request 😜