Hi,
As part of our firmware upgrade (previosuly used external SPI Flash), I am using the upper two arrays (2,3) of a PSOC 5LP to store a new firmware image.
All of the executable code lives in Array0. Here is my problem. It seems as though the CPU stalls during the entire time it takes to write the flash. In the TRM, it seems to indicate that the cache controller and SPC can access different banks (arrays) without conflict. However, if they are in the same bank, the cache controller must wait for the SPC operation to complete.
In my case, there should be no conflict ??? Any ideas ? This causes the rest of the system functionality to fail while the writes finish....
Is there something I am mis-interpreting ?
Thanks in advance
The code is quite simple.
I previously set the ECC buffer and called the settemp functions. The values get written fine.
static uint32 FlashPage256ProgramReadModifyWrite(unsigned long offset, uint8 *buf, uint16 len){ uint8 array=2; uint8 row=0; uint8 byteOffset; uint32 origOffset = offset; cystatus status; if (offset > FLASH_MAX_OFFSET) { return 2; } if (len > FLASH_ROW_SIZE) { return 3; } if (offset > 0x0000FFFF) { ++array; // 4th array offset -= 0x00010000; // adjust offset to account for new array } row = offset / FLASH_ROW_SIZE; // now figure out overwrite data byteOffset = offset - (row * FLASH_ROW_SIZE); FlashRead(origOffset & 0xffffff00, flashTempBuf, FLASH_ROW_SIZE); memcpy((flashTempBuf + byteOffset), buf, len); status = CyWriteRowData(array, row, flashTempBuf); if (CYRET_SUCCESS != status) { return 5; } if (memcmp((void *)((origOffset & 0xffffff00) + FLASH_DOWNLOAD_BASE_OFFSET), flashTempBuf, FLASH_ROW_SIZE) != 0) { return 6; } return 0;}
