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As part of our firmware upgrade (previosuly used external SPI Flash), I am using the upper two arrays (2,3) of a PSOC 5LP to store a new firmware image.
All of the executable code lives in Array0. Here is my problem. It seems as though the CPU stalls during the entire time it takes to write the flash. In the TRM, it seems to indicate that the cache controller and SPC can access different banks (arrays) without conflict. However, if they are in the same bank, the cache controller must wait for the SPC operation to complete.
In my case, there should be no conflict ??? Any ideas ? This causes the rest of the system functionality to fail while the writes finish....
Is there something I am mis-interpreting ?
Thanks in advance
The code is quite simple.
I previously set the ECC buffer and called the settemp functions. The values get written fine.
By the way, it is not obvious by my code above how I know that either the CPU has stalled or interrupts are being disabled. There is an interrupt every 250usec in which I toggle an output. This stops for around 10msec when this call is made in the non-isr context.
Cypress confirmed that the TRM is incorrect. The cache and SPC cannot access Flash at the same time regardless of array or row... Be careful if you are using flash for storage of anything other than code using the bootloader.