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PSoC 5, 3 & 1 MCU

VlYe_281166
New Contributor II

Investigating 16 Bit Filter Operation Example Project(https://www.hackster.io/bmah/psoc-5lp-16-bit-and-24-bit-digital-filter-code-examples-ddcf9c),

I discovered a strange anomaly.

Everything works fine, until you change from channel A to Filter channel B. Almost in all input signal range, the output filter signal is dramatically distored like an overload in the middle of scale. Here are some pictures. First pic. - Ch. B, second one - Ch. A. Yellow - Input, Blue - Output.

In the same time corresponding 8 and 24 bit examples works fineFilt16bit_B_1V.jpgFilt16bit_A_1V.jpg on both channels.

Modified project in attach. To choose between Flter Channels comment/uncomment #define FiltA at the beginning of main.c.

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1 Solution
SampathS_11
Moderator
Moderator

Dalign has to be set for Channel B also. This is the case where the 16 bit input is shifted left by 8 bits. In main.c, we have the following line :

Filter_DALIGN_REG = Filter_DALIGN_REG | FILTER_DATA_ALIGN;

The above line has to be replaced by the following two lines:

Filter_SetDalign(Filter_STAGEA_DALIGN | Filter_HOLDA_DALIGN, Filter_ENABLED);

Filter_SetDalign(Filter_STAGEB_DALIGN | Filter_HOLDB_DALIGN, Filter_ENABLED);

Now both the channels will give the same output.

View solution in original post

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5 Replies
VlYe_281166
New Contributor II

I tested this on 4 boards: 2 FreeSoc form SparkFun with CY8C5888AXI-LP096 and 2 CY8CKIT-050 with CY8C5868AXI-LP035 with the same result. And any project or example with 16bit DMA access to Filter behave similar.

In attach modified example, with switching filter channels on the fly via button.

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SampathS_11
Moderator
Moderator

Dalign has to be set for Channel B also. This is the case where the 16 bit input is shifted left by 8 bits. In main.c, we have the following line :

Filter_DALIGN_REG = Filter_DALIGN_REG | FILTER_DATA_ALIGN;

The above line has to be replaced by the following two lines:

Filter_SetDalign(Filter_STAGEA_DALIGN | Filter_HOLDA_DALIGN, Filter_ENABLED);

Filter_SetDalign(Filter_STAGEB_DALIGN | Filter_HOLDB_DALIGN, Filter_ENABLED);

Now both the channels will give the same output.

View solution in original post

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VlYe_281166
New Contributor II

Very good answer, but as I answered in mycases,

agree, that it was not obvious.

And it was not mentioned elsewhere in examples.

I guess it have to be especially pointed out in the documentation.

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SampathS_11
Moderator
Moderator

Hello Vladimir,

Data Alignment has been explained on page 19 of Filter 2.30 datasheet.

However, we will update the example project in Hackster.io. The line

Filter_DALIGN_REG = Filter_DALIGN_REG | FILTER_DATA_ALIGN;

will be replaced by

Filter_SetDalign(Filter_STAGEA_DALIGN | Filter_HOLDA_DALIGN, Filter_ENABLED);

Appropriate comments will be added.

Hopefully, this change will indicate that if you are changing to Channel B, Data aligment has to be set on Channel B too.

Do kindly let me know your thoughts.

Thanks, and regards,

Sampath Selvaraj

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VlYe_281166
New Contributor II

Thanks a lot, Sampath!

Well done.

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