FIR Filter with 8-Bit Streaming

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MiKa_4247191
Level 1
Level 1
First reply posted First question asked First like given

Hi,

I'm just rebuild the sample project CE58352. It's a FIR Filter 8 - Bit. I think i can transfer the values form the AD converter to the filter, but i don't get a DMA request from the Filter_1 to the VDAC. I tried to debug the project with the UART interface and the code never gets a Status_Reg_2_Read() == true.

I think there is a problem with the DMA configuration. I'm the DMA configuration with the DMA wizzard like the description in the cypress document CE58352

Perhapse someone has an idea what i have made wronge.

Have a nice day

bye by

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odissey1
Level 9
Level 9
First comment on KBA 1000 replies posted 750 replies posted

mika,

This has beed discussed too many times. Please refer to the working projects in the threads below.

The issue with Filter-DMA-VDAC transfer is that the Filter output is signed (int8), while VDAC8 input register accepts only unsigned values (uint8), so some workaround is necessary. If interrupt polling technique is used, then value can be simply incremented by 128u. But no such luck if DMA is used. For that reason either intermediate logic can be used (to XOR highest bit), or ADC input should be limited to a half-range, like 0-to-Vref, or Vref-to-2Vref.

Class D adcDelSig>Filter>Pwm using DMA only

Re: FIR filter example is not working on CY8CKIT-059

Modify ADC DelSig sample values

/odissey1

ADC-Filter-VDAC_01s_01.png

ADC-Filter-VDAC_01s_PWM_01.png

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