Execution of PendSV handler for interrupt

[hata_3396041]

Hello

In the thread

https://community.cypress.com/thread/59115,

Ganesh-san taught me best practices for interrupts.

I am investigating with reference to the current PSoC5LP_Architecture_TRM,but I don't really understand the significance of implementing it using the PendSV handler.

My understanding of this handler.

・Shorts the ISR for interrupts.

・Every time an interrupt occurs, describe the process I want to execute in the first half, put the relatively generous process in the second half,

　　and leave the series of processes to the PendSV handler.

However, considering the contents of the threads discussed so far, the interrupt pending register is cleared when the ISR is executed,

If the same interrupt occurs next time, it should be detected properly.

So I have one question.

●Is the pending register of UART_TXISR sometimes not cleared while ISR of UART_TX_FIFO_EMPTY is being executed?

If this is not the case, I don't think it is necessary to take measures to "exit TX_ISR as quickly as possible".

Or is my idea of PendSV wrong?

Best Regards

Hayato

[AikoO_51 · Accepted solution]

Yes, your understanding is correct, but that’s just one of suggestions to avoid to miss some interrupts.

You can clear a pending states register when it’s entered to ISR. (Pattern 1 as Ganesh mentioned)

Also you can make ISR shorter with PendSV to miss some interrupts. (Patten 4 as Ganesh mentioned)