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PSoC 5, 3 & 1 MCU

mvarga
New Contributor II

Dear Cypress Community,

I am using an evaluation board for PSoC 5LP (CY8CKIT-059) and trying to downmix a signal.

My aim is to downmix a noisy signal that contains a very small sine wave (1mVpp) whose frequency is known, e.g., 10 MHz. The DC value I would get after the mixing+filtering tells me if that sinewave is present in the signal or not.

I was able to achieve this only for sine waves of max. 4 MHz using the mixer component of 5LP. 

Question: Is it possible to mix with a frequency higher than 4 MHz so that I can downmix a 10 or 15 MHz signal?

I ask this because I do not want to include/pay a separate (I-Q) demodulator in my design. 

Cheers,

Matija.

 

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1 Solution
odissey1
Honored Contributor II

Technically, PSoC5 doesn't have analog capability in 10-15MHz frequency range.

I suggest using a simple Tayloe mixer to downsample incoming sine signal. See, for example this YouTube video (closer to the end)

https://youtu.be/JuuKF1RFvBM

There are many other links for Tayloe detector schematic. See.e.g:

http://www.norcalqrp.org/files/Tayloe_mixer_x3a.pdf

https://www.arrl.org/files/file/Technology/tis/info/pdf/020708qex013.pdf

Basically, it is 4x fast analog switch, which is controlled by a pair of quadrature signals I and Q. The output is practically a DC voltage and can be amplified by slow opamps in psoc. Knowing the amplitudes of the quadrature signals, one can calculate the phase of the incoming sine signal.

The analog switch is cheap ($1). So all it needs is to generate a pair of digital quadrature signals I and Q at 10MHz, alongside with the source sine.

 

If the phase of the incoming signal is fixed (for example it is being provided by local signal generator), then Tayloe mixer simplifies even further, as Q component is not needed, and 4xF frequency generator is not needed, etc.

Here is another good link with PSoC5 project using Tayloe mixer by Mike Hightower (attached)

0-500khz Very Low Frequency direct sampling SDR

Can you provide more specifics on the project to help you better?

/odissey1

View solution in original post

21 Replies
odissey1
Honored Contributor II

Technically, PSoC5 doesn't have analog capability in 10-15MHz frequency range.

I suggest using a simple Tayloe mixer to downsample incoming sine signal. See, for example this YouTube video (closer to the end)

https://youtu.be/JuuKF1RFvBM

There are many other links for Tayloe detector schematic. See.e.g:

http://www.norcalqrp.org/files/Tayloe_mixer_x3a.pdf

https://www.arrl.org/files/file/Technology/tis/info/pdf/020708qex013.pdf

Basically, it is 4x fast analog switch, which is controlled by a pair of quadrature signals I and Q. The output is practically a DC voltage and can be amplified by slow opamps in psoc. Knowing the amplitudes of the quadrature signals, one can calculate the phase of the incoming sine signal.

The analog switch is cheap ($1). So all it needs is to generate a pair of digital quadrature signals I and Q at 10MHz, alongside with the source sine.

 

If the phase of the incoming signal is fixed (for example it is being provided by local signal generator), then Tayloe mixer simplifies even further, as Q component is not needed, and 4xF frequency generator is not needed, etc.

Here is another good link with PSoC5 project using Tayloe mixer by Mike Hightower (attached)

0-500khz Very Low Frequency direct sampling SDR

Can you provide more specifics on the project to help you better?

/odissey1

View solution in original post

odissey1
Honored Contributor II

mvarga,

On the other hand, simple NE602 (SA602, SA612) mixer is cheap (~$2), and can be used to downconvert the signal. See this NE602 use example (around 6:00)

https://youtu.be/Mm7WfVzr1ao

 

But I believe that direct conversion with Tayloe mixer is simpler and returns DC output.

/odissey1

mvarga
New Contributor II

Dear odissey1,

I find the Tayloe mixer a very appealing solution for my problem and I will go forward with it. 

Best regards,

Matija.

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odissey1
Honored Contributor II

mvarga,

I am just curious, is this for detection of the radio signal (remote 10MHz oscillator with undetermined frequency and phase) or a lock-in detector (local 10MHz oscillator with fixed frequency and phase)?

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mvarga
New Contributor II

Hi odissey1,

I am injecting some signal on one side of a wire (instead air) and trying to detect it on the other side. I am glad you ask this question because my next open question is how to deal with the fact that the input signal and LO won't have exactly 10 MHz frequency, i.e. input freq. might be 10.08 MHz and the LO 9.92 MHz. My "solution" for now is to sample the down converted signal and then do FFT.

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odissey1
Honored Contributor II

mvarga,

It is better to keep frequencies close. The frequency deviation in your specs is: 10.08MHz - 9.92MHz = 160 kHz. This is a little bit high. For example, if transmitter and receiver are  stabilized using low-grade XTAL with 200ppm accuracy, the frequency deviation will be only 10MHz x 2 x 200E-6 = 4kHz, which is much more manageable. It is convenient to bring this frequency down as much as possible, as it allows using DelSig-ADC instead of SAR_ADC. The DelSig-ADC has high impedance input buffer with variable gain, which potentially allows omitting two Opamps from the Tayloe mixer. The above Opamps should be selected with good noise figures, as PSoC internal Opamps has equivalent noise ~100x worse (~700nV/sqHz).  

The Tayloe detector produces both I and Q components of the incoming 10MHz signal. Since the transmitter and receiver are not synched, both I and Q will oscillate at frequency  F_transmitter - F_tayloe, which is less then few kHz (using XTALs). Total sine carrier amplitude at any given moment is: Ampl = SQRT(I^2 + Q^2).

So, the algorithm of carrier amplitude detection can be following:

(1) measure I and Q outputs of the Tayloe mixer using DelSig-ADC. Both I and Q will be a signed values, oscillating at frequency offset.

(2) Calculate instant amplitude Ampl=SQRT(I*I + Q*Q). A CORDIC component can be used to offload the calculation. The obtained Ampl value is likely to be quite noisy.

(3) Low-pass filter Ampl values for better S/N using the Filter component.

 

To operate Tayloe mixer at 10MHz, the PSoC's MASTER_CLK should run at 40MHz or 80MHz.

Alternatively, external frequency generator si5351 can be used to drive the Tayloe mixer, while PSoC operating at its own frequency. Using external si5351 allows for "scanning the range" if necessary, or tuning between 10/15MHz "on the fly", etc.

/odissey1   

mvarga
New Contributor II

Dear odissey1,

Thank you so much for your advice. I am not only getting very fast to the solution but also learning on this thread.

The deviation between frequencies that I wrote was somehow exaggerated (a worst case). I find it comforting after you showed me that the deviation will not be as  significant as I thought.

In addition, thank you for listing the PSoC components that might be useful for my problem - this will speed me up significantly.

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mvarga
New Contributor II

hi oddisey,

I am trying to use as much internal components of PSoC so this sentence caught my attention:


@odissey1 wrote:

The DelSig-ADC has high impedance input buffer with variable gain, which potentially allows omitting two Opamps from the Tayloe mixer.  


How would such a circuit (without opamps) look like? I understand that there is only 1 DelSig-ADC in PSoC 5, I know how I'd do it with 2 DelSig-ADCs...

mvarga 

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odissey1
Honored Contributor II

mvarga,

This is a schematic extracted from Mike Hightower's paper on PSoC5-based SDR receiver (attached). It shows only the broadband input filter, a balun, a Tayloe mixer, Opamps and PSoC5 inputs. The low-noise Opamps were used to amplify differential voltage from each capacitor pair, which is typically in 10th of uV range, by about 1000 times prior to ADC sampling. If your signal is larger, say in ~10-100mV range, then, I believe, the Opamps can be omitted, using direct sampling of the differential voltage on C11-C14 by DelSig-ADC.

Hightower_Tayloe_01a.png

Here is potential arrangement using external Tayloe mux (P/N SN74CBT3253CPWR). It uses full Tayloe mixer, with input balun and four capacitors. The input filters and protection diodes are not shown. Since the input frequency is fixed (10MHz), it is possible to put a resonant LC fiter to reject all other signals. Note that PSoC5 must have a XTAL installed to maintain its frequency.  

Tayloe_02a_A1.png

The mixer is driven by a pair of (10MHz) I/Q clocks produced by the quadrature generator, resulting in frequency BUS_CLK/4. PSoC5 BUS_CLK should be set to 40MHz in this case. The ADC is set to operate in differential mode with input buffer enabled. It sequentially samples voltage difference on the caps pairs C1/C2 and C3/C4 using Analog Mux (software mode). If BUS_CLK/4 is close to the frequency of the incoming signal (10MHz) to within <100ppm, then capacitor voltages will oscillate at low speed (<1kHz), and ADC sampling can be performed in software code (no hardware AMux is required). 

 

The ADC sampling code can be something like this:

void Init()
{
    ADC_1_Start();
   ADC_1_StartConvert();

}

 

int main()
{
     Init();
     int16 val1, val2=0;
     for(;;)
     {

           .....

           AMux_1_FastSelect(1);
           ADC_1_StartConvert();
           ADC_1_IsEndConversion(ADC_1_WAIT_FOR_RESULT); // Wait until the ADC conversion is complete/
           ADC_1_StopConvert(); // Since the ADC conversion is complete, stop the conversion/
           val1 = ADC_1_GetResult16();

           AMux_1_FastSelect(0);
           ADC_1_StartConvert();
           ADC_1_IsEndConversion(ADC_1_WAIT_FOR_RESULT); // Wait until the ADC conversion is complete
           ADC_1_StopConvert(); // Since the ADC conversion is complete, stop the conversion
           val2 = ADC_1_GetResult16();

           uint16 root = Sqrt((uint32) (val1*val1 + val2*val2)); // get square root

           .....

}

/odissey1

mvarga
New Contributor II

odissey1,

Thank you so much for the detailed answer! The MUX in front of the ADC was my doubt - now all is clear. 

Now I'm curious - how do you create such (component-specific) schematics? You did the graphics manually or those components (e.g. KIT and mux/demux)  can somehow be loaded in PSoC Creator?

 

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odissey1
Honored Contributor II

mvarga,

The drawings are made using freeware community PSoC Annotation Library 1.0

PSoC Annotation Library 1.0 

Attached is a project showing Annotation Library usage. The project is a non-working sketch, it has not been tested. To add Annotation Library to your project, download and unzip archive file, and then Project->Dependencies->User Dependencies->New

/odissey1

Tayloe_02a_ann_A.png 

mvarga
New Contributor II

odissey1,

this looks amazing! Thank you!

 

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odissey1
Honored Contributor II

Thank you. I am currently testing a Tayloe project using various ADCs arrangements. Will post results after weekends.

What signal amplitude (mV) and S/N level are expected at the input of the detector? Is 10MHz a strict number or, say 10.7MHz may suffice? I am asking because there are COTS band-pass filters for some specific frequencies available, which can simplify the schematic and improve S/N considerably. 

 

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mvarga
New Contributor II

I have managed to get the double-balanced Tayloe detector to work. 

I use 4 PGAs to amplify differential signal (with "-" terminals connected together and "+" terminals as inputs). I feed that amplified differential signal into a differential AMux which then feeds into differential input of SigmaDelta ADC.

My frequencies are still not fixed and they can be in the range between 1 and 15 MHz.  My signal amplitude will be 100uVpp (I've tried to amplify a low frequency (200Hz) signal with 100uVpp and it worked well with the above amplifier configuration. Regarding the S/N, I still don't know the exact S/N.

Some open points still remain:

  • Not sure how to choose XTAL nor how to connect to the PSOC5LP KIT-059 such that it reliably works (for now I synthesize my select signal using a signal generator).
  • Sampled signal has an offset of a couple of mV (bias of VDDA/2 is fed at the middle terminal of the input trafo).
  • UART communication is not reliable, often i.e. data + some trash is parsed on my PC (using sprintf to put data into a buffer variable and then UART_PutString to send to PC; data parsing and visualization using SerialPlot app). I believe that the connection between the USB and the devkit is poor.
  • Not sure how to do sqrt(I*I+Q*Q). I've installed the CJCU_Fsqrt component from the list of validated components but I don't know if the data I'm getting makes any sense.

I will try to push Tayloe to the limits: 1) try to detect the smallest possible signals, 2) mix in some noise on top of that and 3) use as little external components as possible. Then I will report my findings here.

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odissey1
Honored Contributor II

1. 

  • Not sure how to choose XTAL nor how to connect to the PSOC5LP KIT-059 such that it reliably works

I use 24MHz XTAL with 15pf load capacitors. It makes huge (>10x) improvement in S/N compared to using PSoC5 IMO as primary clock when working in 1-12MHz range. I believe this is due to the  BUS_CLK frequency fluctuations using IMO, and Tayloe mixer RC frequency cutoff.

This is the XTAL attachment to the KIT-059 board using Pin_15[0] and Pin_15[1]. You can see both XTAL and 15pf caps to the GND (blue line)

KIT-059 with XTAL_24MHz 15pf_01a.jpg

 

Following Clock and XTAL configuration settings were used:

Clocks configuration_01.pngXTAL configuration_01.png

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odissey1
Honored Contributor II

2.

  • UART communication is not reliable, often i.e. data + some trash is parsed on my PC (using sprintf to put data into a buffer variable and then UART_PutString to send to PC; data parsing and visualization using SerialPlot app). 
  • Not sure how to do sqrt(I*I+Q*Q). 

I use SerialPlot for data output in binary (Custom Frame) mode up to 1kHz data rate without issues using custom community component SerialPlot:

SerialPlot: interface to real-time data charts  

It automatically takes care of all formatting of the data packets.

Project also uses a custom square root calculator, which is CPU-based (not UDB). It takes only ~160 processor clocks to obtain the 16-bit result (32-bit internal calculations). The FastSqrt component is already included into the project. 

Project is attached. 

P.S. I am still in process of testing various ADCs, Muxes, etc., so no results yet. It kinda  works at 12 MHz, but I haven't decided what to do with offset shifts for sampled I and Q signals. The plan is to play with analog part and/or use a High-Pass digital filter.  

Figure 1. Tayloe mixer Direct sampling demo using AMuxHw and DelSig-ADC in 12-bit mode. 

Tayloe_ext_02b_A_AMuxHw.png

Figure 2. Using SerilPlot custom component for UART communication with charting software

Tayloe_ext_02b_UART.png

Figure 3. Project annotation using PSoC Annotation Library v1.0

Tayloe_ext_02b_C_KIT-059.png

Figure 4. SerialPlot input data format. Note that v0.10.0 was used, I find the latest one v0.11 is not very stable.

SerialPlot data format_3x int16_01a.png     

 

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mvarga
New Contributor II

odissey1,

Thank you again for your detailed help.

I have managed to go around the offset problem by:

1) using on-off keying with a low frequency (e.g. f_ook = 1/T=1Hz) on the input signal (essentially I've gated the input signal at the signal generator),

2) buffering ADC samples and subtracting the current sample from a sample taken at t-T/2.

Step 2 is essentially a derivative so it doubles the noise amplitude (i.e. multiplies the noise power with a factor sqrt(2) ).

I still have one more optimization question:

1) Which cheaper/simpler PSoC could do the same job (4PGAs, 1 AMUX, 1 ADC, 40MHz CLK)?

I've tried to find in datasheets of both Analog Coprocessor and PSoC 5LP how many resources I have available but without a definite conclusion. I know that 5LP has 4 PGAs.

M

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odissey1
Honored Contributor II

mvarga,

It seems that not much of PSoC hardware is being used, so PSoC4200(M) may suffice. Prices for P4200/P4200M vary $2-4 (single unit), which is much cheaper than PSoC5. Selection table shows that none of the P4200/M has PGAs (Analog block), but it has 2 standard Opamps, and most of P4200M have 4 Opamps. I believe that 2 Opamps working in differential mode should suffice for Tayloe mixer operation. PSoC4 has only one SAR_ADC, which should do. I tested Tayloe mixer using both DelSig-ADC and SAR_ADC in scanning mode, and don't see much difference in s/n as long as channel scanning rate >40kHz. All P4200 series can run up to 48 MHz, and most have scanning SAR_ADC.

Probably that PSoC4100 (/M has DMA) is even cheaper, but usually harder to develop, I would use it only after system is fully debugged using P4200.

/odissey1

PSoC4200_01a.png   

odissey1
Honored Contributor II

mvarga,

There are several PSoC4 kits useful for sensor prototyping, which can be found at  Cypress Online Store. They provide general idea on PSoC4 capabilities and pricing (DigiKey).

1. CY8CKIT-043 PSoC® 4 M-Series Prototyping Kit   chip: CY8C4247AZI-M485, price $3.915 (960pc)

2. CY8CKIT-147 PSoC® 4100PS Prototyping Kit , chip CY8C4145LQI-PS433, price $3.29 (980 pc)

3. PSoC® 4 CY8CKIT-146 4200DS Prototyping Kits , chip CY8C4246PVI-DS402, price $2.17 (1000 pc)

4. CY8CKIT-049-42xx PSoC 4 Prototyping kit (no programmer on kit), chip CY8C4245AXI-483, price $2.17 (960 pc)

5. CY8CKIT-049-41xx PSoC 4 Prototyping kit (no programmer on kit), chip CY8C4125AXI-483, price $1.862 (960 pc)

mvarga
New Contributor II

Thank you!

I was unsure whether they use those OpAmps to implement PGAs. Now is all clear - it's the Analog Blocks that they use.

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odissey1
Honored Contributor II

If you need gain adjustment, one way to do that is to adjust the reference voltage of the SAR_ADC using a VDAC8. It works down to about 100mV.

See test results on the terminal output: ADC code output  vs. Vref (VDAC code)

PSOC 5LP SAR resolution