cancel
Showing results for 
Search instead for 
Did you mean: 

PSoC 5, 3 & 1 MCU

avke_3174516
New Contributor

Dear Sir

we are working with the CPU CY8C5667AXQ-LP040.

we have boards with CPU from 2019 and we use the ADC 12 bit

The transfer function from analog voltage to digital number is not the same as with new components from 2020.

Do we need to calibrate the A2D in each CPU?

If yes is it gain and offset that needs to be calibrated?

can you kindly send me link to reference or white page or software sample  for this issue

thanks

avihoo keret

A2D configuration.JPG

0 Likes
1 Solution
Vasanth
Moderator
Moderator

HI Avihoo,

Kindly check this Application Note. It explains how to calibrate an analog signal chain by using a calibrated Delta Sigma ADC and an on-chip EEPROM that are available in PSoC® 3 and PSoC 5LP. An example of a programmable gain amplifier as part of the analog signal chain is also described. AN68403 shows how gain and offset errors can be eliminated in the entire signal chain.

Best Regards,
Vasanth

View solution in original post

0 Likes
2 Replies
Vasanth
Moderator
Moderator

HI Avihoo,

Kindly check this Application Note. It explains how to calibrate an analog signal chain by using a calibrated Delta Sigma ADC and an on-chip EEPROM that are available in PSoC® 3 and PSoC 5LP. An example of a programmable gain amplifier as part of the analog signal chain is also described. AN68403 shows how gain and offset errors can be eliminated in the entire signal chain.

Best Regards,
Vasanth

View solution in original post

0 Likes
Len_CONSULTRON
Honored Contributor II

avihoo keret,

If you are looking for uber accuracy, it is always best to calibrate each individual board's ADC path with a good reference source.  Vasanth's link should help with the gain and offset and storing it for future compensations when the product reaches the field.

Here is a list of known factors that affect the accuracy of the ADC path.

  1. offset - the vertical shift (+ or -) of the response.  This requires only one calibration measurement. This is particularly true if you change the PGA gain is SW.
  2. gain - the slope of the response.  This requires two calibration measurements.   This is particularly true if you change the PGA gain is SW.
  3. temperature - at a minimum the temperature may effect gain and offset.   This requires at least two calibration measurements. One at minimum operating temp and the other at maximum.  Addition measurement points may be needed if non-linearity is an issue.
  4. INL - Integrated Non-Linearity.  This is the worst-case measurement of the error from a straight line for the full scale count of the ADC result. In theory, the ADC result across the full scale should be a flat line.  The INL error would appear as one or more small curves in what should be flat.  For most ADCs this error is +/- 2 to 4 LSbs.  This factor is usually the accumulation of clusters of DNL (see next bullet).
  5. DNL - Differential Non-Linearity.  This is the worst-case measurement of error between any two consecutive ADC counts. In theory, every x uV should consistently increment or decrement to the next ADC count.  Sometimes this is not always x uV.  This value is usually less than 0.5 LSb and usually not a big concern for most applications.   This requires many measurement points to try to re-linearize the result.

The list above is my recommendation of priority of which calibration factors to approach if you can't do them all.

Offset and gain are particularly important since you are using a PGA as a front-end.   This is because the Cypress PGA although a fine component will add offset and gain error because the resistances used for gain and Vos (input voltage offset) vary from chip to chip.

Temperature is nice to compensate if you can afford to use a temp chamber during the calibration phase.  Most developers will provide a temperature compensation table determined at the design-phase of the project.  Usually these are offset and gain temp comp factors added to the ADC path offset and gain factors determined at manufacture time.  These temp factors don't usually vary by much across the different chips.

The INL compensation is not normally done unless the part is to be used in safety-critical or scientific applications.  If calibration is needed, very many points of measurement are needed.  Usually the entire ADC scale is measured to find the non-linearity points.   As you can imagine, this calibration cycle will take a LONG time to complete.

Here are some simple techniques to speed up the calibration time:

  • Determine the working range of the actual use of the ADC path.  Many times not all the ADC counts need to be uber accurate.  For example, if you are measuring the input supply voltage, ADC converted values below 4V don't need to be that accurate since 4V is the lower threshold.  The same thing can be said for values above the maximum operating voltage.  In general, non-linearity usually occurs at the measurement rails.  Chose the range that best suits the need for accuracy.
  • Perform your offset and gain calibrations at Minimum Operating Voltage - 0.1V and Maximum Operating Voltage + 0.1V.  Going above and below the min and max operating values respectively provides a little margin.

I hope this helps in your design decisions.

Len

Len
"Engineering is an Art. The Art of Compromise."