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PSoC 5, 3 & 1 MCU

Anonymous
Not applicable

 Hi all

   

Please is possible make simple multiplier on datapath ? (example: two input 8bit * 8bit = 16bit output)

   

On the verilog is simple but very big UDB consumtion.

   

Many thanks help and example.

   

Kamil

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Esteemed Contributor

If you do not need parallel speed consider serial multiplication -

   

 

   

http://lcr.uns.edu.ar/ADCD/Documents/Lecture15_multiplicacion.pdf

   

 

   

google "serial 8 bit multiplier", you will get a lot of approaches.

   

 

   

Regards, Dana.

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Anonymous
Not applicable

This verilog module working but is it UDB killer 🙂

   

http://www.altera.com/support/examples/verilog/ver-unsigned-multiply-accumulator.html

   

is possible make this on datapath ?

   

or question serial 8bit multiplier is equivalent ?

   

(my idea is two 8bit sine wave multiplied like FM synthesis)

   

 

   

Thanks Kamil

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Esteemed Contributor

Serial approach feasability depends on your computation rate

   

requirements. If this is being done at audio rates intuition tells

   

me serial approach should work fine. This of course would be

   

a verilog solution.

   

 

   

Regards, Dana.

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Anonymous
Not applicable

 Thanks info Dana

   

Im tested this serial multiplier 

   

http://downloadsourcecodes.com/verilog/verilog-code-for-serial-multiplier

   

working but 80% UDB comsumption 😞

   

DataPath ALU not support multiplification ? Thanks info

   

Kamil

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Honored Contributor II

No, the ALU doesn't support multiplication. But it supports addition, so you can roll this into your own multiplier (though this will be some work). But it should be possible to do 8x8 bit multiplication within two UDBs (which get joined to allow 16-bit-logic)

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Anonymous
Not applicable

 Thanks info Hli

   

Is possible make example ?

   

Many many thanks

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Honored Contributor II

Unfortunately I currently don't have time for that. But since you already have a verilog solution using an adder made out of PLDs, you can use that as a starting point. The working principle is the same, but you use the ALU for the addition and for storage.

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Esteemed Contributor II

The algorithm is straightforward:

   

Acc=0

   

if lowest bit of multiplicant = 1 Add multiplicator to Acc

   

shift multiplicator Left by one

   

shift multiplicant right by one

   

if multiplicant = 0 we are ready, Acc contains the 16 bit result, else go back to the "if" stasement above

   

 

   

Happy verilog / datapath coding

   

Bob

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Honored Contributor II

You might want to read this post for an explanation how to use / configure the data path FIFO as a single register.

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