PSoC 5, 3 & 1 MCU

[Anonymous]

 Hi all

   

Is possible help me with simple parallel datapath component ?

       

My idea is 8bit PWM ( like simple deltasigma DAC ) 

   

1x clk input

   

1x 8bit data input

   

1x 1bit pwm/dac output

       

Is possible in datapath ? (for less consumption UDB than verilog PWM)

       

Many thanks help

       

Kamil

[JoMe_264151]

You asked "Is possible in datapath ? (for less consumption UDB than verilog PWM)"

   

It is possible, and it will probably take one UDB but you will need to use verilog, what else.

   

So what do you want to perform that the UDB-based PWM cannot do?

       

Bob

[Anonymous]

 Thanks reply

       

My project require more UDBs datapath is ideal for save this.

       

Please help me how to make parallel input datapath.

       

Many thanks

[JoMe_264151]

When you look into the PWM v2.4 datasheet under "Resources" you will see that the 8-bit version takes 1 datapath, so you cannot do less than that.

   

When you want to do a working PWM yourself, you will need verilog and you have to understand how a datapath works and what connections exist. Very helpful is the "DataPath Cheat Sheet" www.cypress.com/

   

Within the DataPath is an 8-bit ALU which you will have to program performing your desired actions.

   

in startmenu under All Programs -> Cypress -> PSoC Creator 3.0 -> Component Development Kit you will find some more documentation.

       

Bob

[Anonymous]

 Is possible modifi PWM 2.4 component to 8bit input ? (this component use only c API not direct input)

       

Thanks info

[Anonymous]

 Před nějakým časem já dělat Verilog PWM komponentu - v pořádku, ale required mnoho prostředků.

[JoMe_264151]

That is truely possible, there is a parallel input for the DataPath. Make sure to work on a copy and change the names of the required files accordingly.

       

Bob

[JoMe_264151]

The amount of resources VeriLog consumes depends only on the resources you really use. Creator is optimizing the needed items as much as possible, sometimes ending in optimizing-out complete components when you do not use its outputs, No joke!

       

Bob