I am working with the latest version of the PSoC technical reference manuals.
PSoC® 5LP Registers TRM
(Technical Reference Manual)
Document Number. 001-82120 Rev. *G November 6, 2019
PSoC 5LP Architecture TRM
(Technical Reference Manual)
Document No. 001-78426 Rev. *G November 6, 2019
It looks compared to the previous versions the only change seems to be an added Infineon logo.
As a result, all page numbers are shift one page.
But even worse references to tables are misaligned in the Registers TRM
Now the reference from a bitfield points to the wrong table. This is very confusing.
Where can I find an explanation DSI fabric the information of the following registers is not very clear:
DSI[0..15]_HC[0..127]
DSI[0..15]_HV_L[0..15]
DSI[0..15]_HS[0..23]
DSI[0..15]_HV_R[0..15]
DSI[0..15]_DSIINP0 - DSI[0..15]_DSIINP5
DSI[0..15]_DSIOUTP0 - DSI[0..15]_DSIOUTP3
DSI[0..15]_DSIOUTT0 - DSI[0..15]_DSIOUTT5
DSI[0..15]_VS0 - DSI[0..15]_VS7
The documentation does not explain how peripherals and I/O pin connect the DSI.
Can you supply me with the correct documentation?
Best regards
Carl
