Creating a Signal Delay in Hardware

[KyTr_1955226]

Hey all,

I have a project I'm working on for PSoC5LP where a typical TTL high/low signal (a POWER_OK signal) is generated by the PSoC after a hardware event (3 POWER_GOOD signals all logic high) occurs.  The catch is that the output signal must be delayed before outputting to a PSoC GPIO.  Not a quick delay like a debounce, but between 500ms and 1s from the signals all being high to PWR_OK asserting high.  Doing something like this in firmware would be pretty simple, but I wanted to accomplish this in hardware.  Here's what I came up with myself, using a control register to simulate the POWER_GOOD signals:

The above solution will delay both the rising/falling edge of the ANDed POWER_GOOD signals from appearing on PWR_OK until the timer period has elapsed, and seems to work well enough, although it's not completely in hardware (the timer must be enabled in firmware).  I'm curious if this is the best way to go about it, of if this could be done more simply or in a more flexible fashion (I.E. would it be possible to modify this so only the rising edge or falling is delayed, but the other is instant?).

Thought this might be an interesting problem to share and see what people can come up with.

[RodolfoGL]

Does the delay need to be configurable and/or precise?

If not, you could use a shift register running at every low frequency.

[KyTr_1955226]

Interesting idea, I hadn't considered a Shift Register.  In this specific instance the accuracy is not vital, so long as it is a delay somewhere between 250ms and 1s.  The delay would be configured at build time, no need to change it at run time. 

I suppose I could get similar functionality from a debounce component with a very slow clock as well.

[Len_CONSULTRON]

KyTr,

A Debouncer component is potentially very good solution.

If you place a 4Hz clock, you get a minimum 250ms signal output.  A 2Hz input, a 500ms output, etc.

[Len_CONSULTRON]

KyTr,

I looks like you came up with a workable circuit.   Yes TMR_SIG_DELAY needs to be started.  This is a very minor concession.   It is basically a near 100% HW solution.

Does this circuit need to implement a multi-trigger on the source input?

Rodolfo's suggestion about a shift register should allow you to eliminate the Start() function.

Rodolfo had some additional questions useful for alternate implementations. 

[KyTr_1955226 · Accepted solution]

Possible idea for delay on rising edge and no delay on falling edge.  Could be modified for the other way around (No delay on rising edge, delay on falling edge):