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PSoC 5, 3 & 1 MCU

crhoc_2121991
New Contributor II

Folks,

I want to extend the functionality of the CyControlReg component by cloning the component and modifying it's verilog. I found the content files here, "PSoC Creator/4.2/PSoC Creator/psoc/content/CyPrimitives/CyPrimitives.cylib/CyControlReg_v1_80". How do I copy/clone/export/??? this component, rename it, modify it then use it in a design. I hope this isn't a newbie question but I did try to figure this out before posting here.

Thanks,

Craig

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1 Solution
RyanZhao
Moderator
Moderator

Hi Craig,

You could import the customized component with following steps:

1. Create a Library project in /clone/export in your workspace;

2. Import CyControlReg_v1_80 Component from Cyprimitives to the created library;

3. Right-click on your workspace name, select Dependencies dialog, check 'Components' and 'Code' of the created library in the dialog.

Attached project is FYI.

More information about export and import component, you could watch these videos:

http://www.cypress.com/training/psoc-video-tutorial-series-how-create-custom-components

Thanks,

Ryan

View solution in original post

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7 Replies
RyanZhao
Moderator
Moderator

Hi Craig,

You could import the customized component with following steps:

1. Create a Library project in /clone/export in your workspace;

2. Import CyControlReg_v1_80 Component from Cyprimitives to the created library;

3. Right-click on your workspace name, select Dependencies dialog, check 'Components' and 'Code' of the created library in the dialog.

Attached project is FYI.

More information about export and import component, you could watch these videos:

http://www.cypress.com/training/psoc-video-tutorial-series-how-create-custom-components

Thanks,

Ryan

View solution in original post

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crhoc_2121991
New Contributor II

Ryan,

Thanks for the videos link.  I tried to watch these on YouTube yesterday but I couldn't figure out the order or how many were in the series. There's not a playlist for them or are they numbered. No worries.

So I looking the link you sent, I can see that I missed some. I'll rewatch these this evening in the correct order, then follow the step above.

Thanks,

Craig

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crhoc_2121991
New Contributor II

Ryan,

I was able to create a library and import the CyControlReg as you outlined in the steps above. I quickly discovered CyControlReg implementation is far more complicated than I assumed. Looks like it a perfect opportunity to learn more about PSoC component development. Thanks for the solution.

Craig

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odissey1
Honored Contributor II

Craig,

what functionality you want to add to CReg?

/odissey1

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crhoc_2121991
New Contributor II

I'm working a CNC project to control stepper motors. Some motor drivers want a setup time if direction signal changes before accepting a step signal, like 50uS. I figured CReg mod could add this delay in hardware.

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odissey1
Honored Contributor II

Craig,

Several solutions are possible (with and w/o CReg), depending on the required accuracy of the '50us' delay. I guess that you want to write 1 to an output pin in the code and have pin to go UP 50us later.

1. Use DFF (flip-flop) after CReg, attached to 20kHz clock. Single DFF pulse delay will vary 0-50us. Two DFFs in series and 10kHz clock yield delay 25-50us, etc. More DFFs - better accuracy. The CReg can act as single DFF if configured in Sync mode.

2. Can use a ShiftRegister component, 8-biit mode (no CReg required). Just write Shift register value, and the output signal will be delayed by 8 clocks.

3. Using Timer in single-shot mode. The pulse delay can be controlled by counter base and clock.

4. Using Count7 down counter in single-shot mode.

5. Using DMA and circular buffer to delay data written to a pin. Delay time then is defined by buffer length and DMA clock.

Posting a link to the controller datasheet would be helpful.

/odissey1

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crhoc_2121991
New Contributor II

Odissey1,

Thanks for all these ideas. I should have posted the project. I'm helping Bart Dring with his grbl port to PSoC5, GitHub - bdring/Grbl_USB_Native: A PSoC5 port of Grbl with native USB support

If you open his project to TopDesign/Steppers, you'll see Control_Reg_Step (which is has a pulse output) and Control_Reg_Dir. He wants to delay the step pulse only if dir output after dir output changes.

I'll think more about your comments and try to figure out a simple solution.

Craig

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