All: I'm looking for VERY specific info/answers, not generalities here. Per HLI's lead, I went and looked at the Sensei blog, and way back in '09 , he did a project using Indexed DMA. Basically, the first TD loads an address into the second TD, and the second TD then moves the actual data where it needs to go. You can consider it a dynamically configured DMA, which is FAR, FAR more powerful and useful in my opinion than a static DMA.
Okay, from that project, I find that he uses the following destination address for the TD DMA register:
1) First question: is the DMA config memory configured as a struct? If so, where can we find a prototype of this struct so that we can understand the elements within it?
2) Why do we see this mix of upper and lower case? Surely there is some sort of method behind the madness of this lexigraphy/syntax.
Okay, I'm going to answer part of my own question here. By the way, I'm using a PSoC 5.
First of all, the DMA configuration is NOT saved to SRAM, there are indeed static registers. If you look in cydevice.h you will see cydev_phub_tdmem#_base defined as 0x40007800.
In CyDmac.h you will find the prototype for the structs dmac_tdmem and dmac_tdmem2.
The dmac_tdmem struct has two array (of uint8) elements, TD0 and TD1.
From CyDmac.c, it appears that there is an array of these dmac_tdmem structs.
It also appears that:
1) dmac_tdmem.TD0 contains an index to the next free Td...but it also seems to be related to the transfer count (there are apparently 12 bits associated with that). Anyone care to explain how this works?
2) dmac_tdmem.TD0 contains the "pointer" to the next Td (it's a uint 8, so it's just the TD handle).
3) dmac_tdmem.TD0 contains a configuration byte (with things like endian swap enable, swap size, increment source or destination address ,etc.).
4) dmac_tdmem.TD1 contains the lower 16 bits of the source address
5) dmac_tdmem.TD1 contains the lower 16 bits of the destination address.
6) I don't see anywhere that the dmac_tdmem2 struct is used in CyDmac.c, even though its elements are self-explanatory! Go figure.
DMAC_TDMEM[td handle].TD1 and DMAC_TDMEM[td handle].TD1 are the LSB and MSB respectively of the upper 16 bits of the source;
DMAC_TDMEM[td handle].TD1 and DMAC_TDMEM[td handle].TD1 are the LSB and MSB respectively of the upper 16 bits of the destination.
Sorry, I meant to say the lower 16 bits, not the upper. The upper 16 bits are actually the base address and that goes into the channel configuration buffer, not the td buffer.
I wanted to address what the "td handle" is. It is a uint8 that is returned by the CyDmaTdAllocate() function...it's an identifier (index?) of the specific td. There are a total of 128 Tds that can be used by the 24 channels.
Can someone help in porting the indexed DMA example (DDS) presented by the seinsei blog from PSoC3 to PSoC5LP ?
I'd appreciate some explanation, how this is working.
What exactly do you want to know? The workings of the DDS itself are explained in the PSoC Sensei blog article. Or do you want to get ehlp on how to migrate this project over to PSoC5LP?
Hli, tnx for the reply.
I have opened Bradleys "indexedDMA" example in Designer 3.0, then changed the silicon to my current platform, which is the CY8C5868AXI-LP035 from freeSoc. There were some errors after building, which I have managed to overcome.
After having programmed the device, there is no sine wave appearing as it should.
There is the PhaseAccum component. And there is the DMA setup code. Junks not directly obvious how they work. I have not invested time yet to beginning digging into the code which obviously I should in order to understand.
Bradleys example has used PSoC3: are there mayor differences between PSoC3 and 5LP which prevent the direct code port from one to the other processor ?
If your hints could accelerate the success of letting run the example, I'd become encouraged to dig into the DMA topic !
Many thanks: Thomas
I used this component on the PSoC5 without problems. So you might want to look at the PSoC5 to PSoC5LP migration guide (or on the one for PSoC3). But I don't see anything in there which could cause that problem. Did you change the DMA setup to accomodate for the differences between PSoC3 and 5?
Maybe you can post your project here so we can have a look...
tnx for being ready to have a look into "my" project.
And tnx for the hint to check for differences between PSoC3 to 5LP
I have not changed DMA setup. Maybe you can quickly see where problems lay ?
Have a good day
If you did not change the DMA config that thats propably the problem. PSoC3 handles the memory different than PSoC5. See AN52705, Page 12 / 14 about this (I remember reading a more torough explanation but cannot find it right now - maybe just read the DMA data sheet).
For uploading the project, try another browser. I had no problems using Firefox so far, but YMMV.