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PSoC 5, 3 & 1 MCU

MaMi_1205306
Honored Contributor

Hi,

We would like to confirm the Counter component for UDB mode.

(1)

When the interrupt condition is "On_Capture",

How long is the interrupt output pin delayed after the capture edge is met?

(2)

How long is the response time of the Counter_ReadCapture() API?

PSoC5LP Capture timing of Counter(UDBmode)

We have synchronized digital circuits according to related articles in the past.

(a) Count by Counter component
(b) Capture the result by Capture edge input
(c) Capture asynchronously by software (Because to avoid metastability from the above link)
(d) Reading counter value in API

It is processed by the above-mentioned flow.

In the case of high-speed counting, the count value may shift infrequently.

Capture is metastable,

The firmware is reading asynchronously while counting,

I am getting count value during capture,

We do not know which of the above is the problem,

Count => Capture => Read count value

We would like to do the above series of processing.
However, can this counter component not be realized if synchronized?

Do you know the best way?

Regards,

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2 Replies
Ekta
Moderator
Moderator

Hello,

To measure the response time of the Counter_ReadCapture() API, you can toggle a digital output pin before and after the API is used. You can then use an oscilloscope to measure the time in between.

"In the case of high-speed counting, the count value may shift infrequently" , Can you tell what count values you are getting at the output.

Thanks

Ekta

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TakashiM_61
Moderator
Moderator

Since this thread has not been responded for long time, this has been locked at this time due to tracking issue appropriately.

It would be appreciated if you post the new thread for further discussion.

Thank you very much for your comprehension for this.

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