cancel
Showing results for 
Search instead for 
Did you mean: 

PSoC 5, 3 & 1 MCU

Len_CONSULTRON
Honored Contributor II

Hi,

I've got a design where I'm using a DMA with a 16bit FF timer.  In the application, I'm reading the counter/capture register with the DMA and storing it to RAM.

In this design, I configure 1 TD with a 2 byte transfer from the counter/capture register.  It's working.

For reasons not stated here, I've considered changing the 16bit FF timer to a 16bit Basic_Counter component and placing 2 Status Registers connected to the counter's outputs.  However, if I use the DMA to transfer the contents of the Status Regs, I would have to implement 2 chained TDs in the same drq since there is not guarantee that the Status Reg addresses are contiguous.

I leave it for the wisdom of the 'cloud' of forum users:  Which is 'best'?

Note: This would apply to PSoC3, 4 or 5.

Len

Len
"Engineering is an Art. The Art of Compromise."
0 Likes
1 Solution
odissey1
Honored Contributor II

Len,

Attached is example project showing FIFOin in 16-bit (2x8) mode with DMA to RAM tranfer and supplemental librraries

FIFOin (PSoC Sensei), LPFilter, ADC_SAR_ex_lib and plotting software Multichart.

/odissey1

Fig.1. Triggered acquisition demo with h/w exponential filtering and decimation. When energized (CReg_Ready),

system waits for h/w trigger, acquires 1000 data points in RAM and plots result using Multichart s/w.  

ADC_LPF_FIFO_03_A.png

Fig.2. Multichart output.

ADC_LPF_FIFO_03_40kHz.PNG

View solution in original post

0 Likes
9 Replies