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I've got a design where I'm using a DMA with a 16bit FF timer. In the application, I'm reading the counter/capture register with the DMA and storing it to RAM.
In this design, I configure 1 TD with a 2 byte transfer from the counter/capture register. It's working.
For reasons not stated here, I've considered changing the 16bit FF timer to a 16bit Basic_Counter component and placing 2 Status Registers connected to the counter's outputs. However, if I use the DMA to transfer the contents of the Status Regs, I would have to implement 2 chained TDs in the same drq since there is not guarantee that the Status Reg addresses are contiguous.
I leave it for the wisdom of the 'cloud' of forum users: Which is 'best'?
Note: This would apply to PSoC3, 4 or 5.
Len "Engineering is an Art. The Art of Compromise."