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PSoC 5, 3 & 1 MCU

quinnd
New Contributor

I am interested in performing amplitude modulation as outlined in this document:

https://www.cypress.com/file/119731/download

The message I need to modulate is sinusoidal and centered around 0V, exactly like in the above document. But from what I've gathered, PSoC I/Os cannot accept or output a negative voltage. Is this correct? If so, how could it be possible to do AM as the application note shows?

By the way, I need to do DSB-SC modulation.

Thanks

Quinn

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1 Solution
BiBi_1928986
Valued Contributor

Hello Quinn.

Have a look at the Cypress video for this app note.  Around time stamp 2:10 to 2:56.
AN62582 - AM Modulation and Demodulation (cypress.com)

There, you will see an explanation of adding an offset to the input 'message' signal, prior to hitting the GPIO pin.

What's not shown in app note (nor video), is how to add this offset voltage to the message signal.  For this, you'll have to do some research applicable to your project.  Generally, it's done with an op-amp.

Good luck with your project.

View solution in original post

2 Replies
BiBi_1928986
Valued Contributor

Hello Quinn.

Have a look at the Cypress video for this app note.  Around time stamp 2:10 to 2:56.
AN62582 - AM Modulation and Demodulation (cypress.com)

There, you will see an explanation of adding an offset to the input 'message' signal, prior to hitting the GPIO pin.

What's not shown in app note (nor video), is how to add this offset voltage to the message signal.  For this, you'll have to do some research applicable to your project.  Generally, it's done with an op-amp.

Good luck with your project.

View solution in original post

odissey1
Honored Contributor II

quinnd,

The input message signal (500Hz sine in the demo project) should be centered around Vdda/2, because that is the voltage provided to the Mixer's reference pin

Screenshot_20210717-204653.png

The simple method to offset the zero-centered signal is to use decoupling capacitor as shown on the figure below (ADC input section)

SAR-Filter-VDAC_signed_FIFO_02a_A.png

 /odissey1