Accessing UDB datapath register A0

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Anonymous
Not applicable

I need a 32-bit counter with multiple compare outputs. I used the UDB editor to quickly generate a verilog file for a 32-bit counter with 1 compare output. I thought I'd edit the verilog file to add more compare outputs but I cant figure out how to access register A0 of the datapath.

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Bob_Marlowe
Level 10
Level 10
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In "Component Author Guide" you find  in section 6.4 all the names to access the UDB registers.

   

Register A0 would be named  Component_<Datapath Name>__A0_REG.

   

 

   

Bob

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Bob_Marlowe
Level 10
Level 10
First like given 50 questions asked 10 questions asked

In "Component Author Guide" you find  in section 6.4 all the names to access the UDB registers.

   

Register A0 would be named  Component_<Datapath Name>__A0_REG.

   

 

   

Bob

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Anonymous
Not applicable

Section 6.4 is about generating the api header file but I wanted to access the a0 register in the Verilog definition of the component itself. Instantiating the datapath module allows you to connect inputs and outputs of the datapath but I cant find any info on how to directly access register a0 in verilog so that I can generate more compare outputs using the plds.

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Bob_Marlowe
Level 10
Level 10
First like given 50 questions asked 10 questions asked

Enter "Cheat sheet" into the keyword search field on top of this page. There is one for UDB dataflow.

   

 

   

Bob