ADC is saturating the lower limit

[OsFe_2822791]

Hello,

I am trying to generate a differential test signal to send to PC by UART and I based on CE95316 but using interruptions. I designed a instrumentation amplifier with gain 1 therefore is transparent in this case (I will use it in next steps), my problem is in Vref because always is saturating in the lower limit as in the picture when Vref=Vdda/2. I also attach the project. Does anyone know why always ADC limits the lower limit and how to fix it?

Thank you in advance.

Regards.

[Len_CONSULTRON]

Oscar,

Take a look at my comments in RED.

Recommendations:

1. You might need to port the Vref of the PGAs out to pins to add a Rgain resistor.  This will be evident by the E1_preout and E2_preout voltages.
2. You might need to flip Opamp_1 so that the '+' terminal is on E1_out.  The sine voltage on IA_out will determine the need to flip.

Update: Corrections 12.20.20

Len

[Len_CONSULTRON]

Oscar,

I used LTSpice to simulate your inamp circuit.

Update" Corrections 12.20.20

Here is the sim results:

My sim results replicate your results.   This issue is In1 amplitude is larger than In2 and In1 is on the '-' terminal of U3.  The difference is In2 - In1.  Therefore, IA_out will be negative through part of the wave which the PSoC being single-ended cannot support.

Solution #1

Switch the input terminals on U3.  E1_out goes to '+' and E2_out goes to '-'.

Sim results:

Solution #2

Here's a better solution that doesn't risk saturating on Vdd.

Move the offset ofIn2 to 0.7V.

Sim Results:

Solution #3 (as proposed by /odissey1)

Instead of GNDing R6, set it to Vdd/2

Sim Results

Len

[odissey1]

Len,

Can situation be solved by connecting R6 (LTSpice schematic) to Vdda/2 instead of GND?

/odissey1

[odissey1]

OsFe,

Why do you need diff amp? Use instead DelSig-ADC, which already has differential input.

/odissey1

[Len_CONSULTRON]

/odissey1,

I agree.   However, I believe OsFe want to eventually use the gain available to the PGA.   IYHO, can he skip Opamp_1 and feed E1_out and E2_out directly into the diff input of the DS_ADC?

Len

[OsFe_2822791]

Hello,

thank you for your response @LePo_1062026 and @BoTa_264741, they were really useful. I change the input voltage to force the v2-v1=+, now values are v2=1.0Vpp and 0.5 offset and v1=0.7Vpp and 0.5 offset. In other hand, this is a simulation with a known signals but in the future I will use this design to adquire ECG/EMG signals so I won´t know if v2>v1, this is the reason I would like to introduce an offset to make this signal always positive at U3 (opamp_1). I use the opamp_1 with the external circuit to generate the gain because I will use PGAs with G=1 without external Rg.

I tried to put R6 to 1.024V, now is the Vref value because I put the input range in ADC among 0 and 2.048V. Now the output is not saturated but is not working well because the result signal it would be 0.3Vpp and it´s 700Vpp and has an offset of 700mV. I design the project acording to the circuit whitch Len simulate, is there something wrong? I attach v1,v2, the top design and the result signal. If it would be necessary I could attach again the bundle project.

Thank you.

Regards,

Oscar.

[Len_CONSULTRON]

Oscar,

I re-simulated your circuit with the 1.024V and adjust inputs.

Here's my Sim output results.   I get a 0.3Vpp with an offset at 1.024V.

Suggestion.

Try this circuit as suggested by /odissey1

The differential mode on ADC_delsig_1 should be able to replace the summing opamp in the inamp configuration.

Len

[OsFe_2822791]

Hello Len,

thank you for your time and re-simulate the circuit, I calculated the Vout by hand as old  school, but results are the same vout=(v2-v1)*(R3/R2)+vref. Related to the design, all seems good but really works bad, do you know what could be the reason to generate the result signal that I shared with this offset and the 700Vpp?

In other hand, the design that you and @BoTa_264741 propose with test signals works well, I will test with real ECG or EMG signals to see if the gain is enough.

Thank you so much.

Regards.

[Len_CONSULTRON]

OsFe,

You're welcome.  

Related to the design, all seems good but really works bad, do you know what could be the reason to generate the result signal that I shared with this offset and the 700Vpp?

If this is the IA_out, I'm not sure what you find wrong. This is a sine wave with 700mVpp with an offset of ~1.024V as predicted by my simulation.

In other hand, the design that you and @BoTa_264741 propose with test signals works well, I will test with real ECG or EMG signals to see if the gain is enough.

Obviously the goal of any input gain is to yield a reasonable signal.  The downside of gain is it will also amplify any unwanted noise present in the signal.

A standard practice is to place an RC low-pass filter in the front end to knock down noise outside of your frequency band of interest.  The lower the frequency that you can tolerate the better.

This can be done with external R and C on each input.  To minimize phase delays between the differential signals I recommend the same value 1% resistors and C0G type caps.

Len

[OsFe_2822791]

Hello,

thank you again for your response, I really apreciate it. I mean the result signal is wrong because it has 700mVpp but you obtain 300mVpp, the gain is 1 in all my circuit so I don´t understand why I get double. Do you know what could be the reason?

Regarding the filtering, since I will adquire ECG/EMG signals I thought use the Filter block to design a 1Hz Butterworth High Pass after the ADC. Is it a good idea or it´s better an RC circuit?

Thank you.

Regards.

[Len_CONSULTRON]

OsFe,

I mean the result signal is wrong because it has 700mVpp but you obtain 300mVpp, the gain is 1 in all my circuit so I don´t understand why I get double. Do you know what could be the reason?

I understand now.   You're right.  1.0Vpp - 0.7Vpp = 0.3Vpp.   It's almost like you're measuring E2_out only.

Hmm.   I'll have to think more about that.

Regarding the filtering, since I will acquire ECG/EMG signals I thought use the Filter block to design a 1Hz Butterworth High Pass after the ADC. Is it a good idea or it´s better an RC circuit?

A high-pass at 1Hz can be done after the ADC.   I was speaking on an external low-pass to minimize the incoming signal noise.

Len

[odissey1]

OsFe,

Please note that at Gain=1, the PGA internal resistor is not connected to anything. Though the Vref terminal of the PGA is shown, no actual connection exist. This is likely a bug.

/odissey1

 

[Len_CONSULTRON]

/odissey1,

I believe the resistor you are referring to in Gain=1 is Rb = 0 ohms as seen in the PGA schematic in the datasheet.

Len

[odissey1]

Len,

Thank you for correcting me. But the net effect is such as the external terminal Vref and Rb become irrelevant. I tested PGA with gain=1, and the output is insensitive to the voltage supplied to Vref input in the entire 0-Vdda range.

/odissey1

[OsFe_2822791]

Hello,

as I said before, I´ve notice that something is wrong because I changed the inputs and WaveDac1 has 0.7Vpp and 0.5V offset and WaveDac2 has 0.8Vpp and 0.5V offset but I always obtain 0.3Vpp. The value of all resistors is 10kohm and all wires all ok. It could be due to that you´re saying? How can I fix it? Thank you.

Regards.

[Len_CONSULTRON]

Oscar,

Have you solved the 700mVpp issue yet?

My results on paper and in simulation are 300mV.   I haven't tried to wire-up the circuit as you designed.

It is possible that a wrong value on R_1, R_2, R_3 or R_4 or a wiring error might cause added gain to the circuit.

Len

[OsFe_2822791]

Hello all,

thank you for the replies. Sorry for delay, I was testing some things with no results. I´ve notice that something is wrong because I changed the inputs and WaveDac1 has 0.7Vpp and 0.5V offset and WaveDac2 has 0.8Vpp and 0.5V offset but I always obtain 0.3Vpp. The value of all resistors is 10kohm and all wires all ok, it could be any wrong configured in the project? Thank you.

Regards.

[odissey1]

OsFe,

I don't see benefits of adding inst amp circuit in front of the DelSig-ADC. The ADC already has differential buffer with variable gain. Another point, the two WaveDacs are not starting simultaneously, so there is some phase difference in output signals.

You can check a similar project

DelSig_ADC - Filter - VDAC streaming demo using DMA

/odissey1

[Len_CONSULTRON]

/odissey1,

Good point.  The ADC_Delsig has up to a 8x gain.

Oscar,

Is 8x good enough for amplification?

Len

[OsFe_2822791]

Hello,

thank you for your response. The main objective to use an aditional opamp is to design an instrumentation amplifier with 3 operationals in PSoC and have more gain than ADC buffer. As Len said, the design is correct, do you know what could be the reasonf for the wrong signal in my test?

In other hand, as I said in the previous response to Len, I will test the circuit with ADC in differential mode to see if the gain if enough, I will inform.

Thank you so much.

Regards.

[EvPa_264126]

Hi Oscar.

You write that in the future you will use this design to receive ECG / EMG signals.

This means that you have to get rid of the constant component of the signal, because real signals have a huge (up to hundreds of millivolts) offset.

In this case, you may be satisfied with the simpler option:

Regards, Eugene.

[OsFe_2822791]

Hello,

I´ve tested something similar but doesn´t work. Could you share your project? Thank you so much!

Regards.

[EvPa_264126]

This is a very ancient Project for PSoC Creator 1.0: ECG_PGA.zip   It is located here.

Have you considered ready-made solutions? for example AD8232.

[OsFe_2822791]

Hello,

thank you for share your project and the reco of AD8232​ , related to this device, do you know if it´s also useful for EMG? Thank you.

Regards.

[EvPa_264126]

Hello.

I was not specifically interested in the EMG problem.

One of the answers is here.

I've read that EMG measurement kits cost a lot more, but not much better.

The main problem with the AD8232 for EMG seems to be very loud noise.

One of the projects (Russian) AD8232 ECG -> EMG uses a special filtering algorithm. The author gives some clarification here.

Project itself: github

Evgeniy.