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Simple trick allows to avoid PSoC Cteator timings limitations in ADC clocking. 1. We need to use external clocking. 2. We need to break direct clock path to ADC, so the Creator will not know about the exact clock frequency. It could be done with any logic element such as AND, OR, NOT etc. In my case most suitable was Either Edge Detector. At my setup with Master Clock 80 MHz, maximum achieved clock to ADC was 26.6 MHz. And it works, giving sample rate ~1.9 Msp/s. Using this technique and double sampling I could digitize in real time Full HD video with 42 samples per string. Some pictures attached. And as usual you'll use it at your own risk.